发明授权
- 专利标题： Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers
- 专利标题（中）： 在形成可变厚度栅极层期间减少对浅沟槽隔离区的注入损伤的影响的方法
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申请号： US10216425申请日： 2002-08-08
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公开(公告)号： US06569739B1公开(公告)日： 2003-05-27
- 发明人: Arvind Kamath , Venkatesh P. Gopinath
- 申请人： Arvind Kamath , Venkatesh P. Gopinath
- 主分类号： H01L21336
- IPC分类号： H01L21336
摘要：
Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.
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