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1.发明授权公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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2.发明授权Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate 失效在氮化衬底的湿氧化下在半导体衬底上形成反熔丝的方法公开(公告)号：US07026217B1
公开(公告)日：2006-04-11
申请号：US10697446
申请日：2003-10-29
IPC分类号： H01L21/336
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28211 , H01L21/2822 , H01L21/28238 , H01L21/76224 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.
摘要翻译： 制造反熔丝的方法包括通过离子注入装置将氮引入衬底。 然后在湿氧化环境中在氮化衬底上形成氧化物介电层。 控制离子注入和氧化的条件以产生具有均匀厚度的电介质和当受到高电场时的低击穿电压。
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3.发明授权Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权制造具有低沟槽寄生电容的浅沟槽隔离结构的方法公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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4.发明授权Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译： 提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。 工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。 选择对应于下部和上部介电材料的厚度的一系列有效介电常数。 下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层， 层隔离结构。
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公开(公告)号：US06586814B1
公开(公告)日：2003-07-01
申请号：US09735084
申请日：2000-12-11
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
摘要翻译： 在活性组分区域之间的半导体晶片中形成浅隔离沟槽，以将活性组分彼此电隔离。 隔离沟槽主要由形成在晶片中的凹部中的绝缘材料（例如氧化物）形成。 诸如BTBAS氮化物的耐蚀刻材料放置在凹槽中的绝缘材料上。 耐蚀刻材料保护绝缘材料免受由于随后的半导体制造工艺步骤的侵蚀，因此通常保持隔离沟槽的完整性和晶片的平面性。
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6.发明授权Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers 有权在形成可变厚度栅极层期间减少对浅沟槽隔离区的注入损伤的影响的方法公开(公告)号：US06569739B1
公开(公告)日：2003-05-27
申请号：US10216425
申请日：2002-08-08
IPC分类号： H01L21336
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/76237 , H01L21/823481
摘要： Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.
摘要翻译： 本发明的实施例包括用于覆盖离子注入半导体衬底表面以在表面的所需部分上引起均匀损伤的方法，从而减少由表面材料的变化蚀刻速率和表面清洁期间的条件引起的不均匀的蚀刻效应。 本发明包括提供具有形成在其上的预定厚度的栅极氧化物区域和牺牲氧化物层的半导体衬底。 衬底的表面被图案掩模以露出栅极氧化物区域中的开口，并且通过图案掩模中的开口注入离子以形成栅极氧化物区域。 从衬底去除图案掩模，并执行牺牲氧化物层的覆盖注入。 然后清洁衬底以除去离开衬底的牺牲氧化物层以备进一步处理。
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7.发明授权Circuits and methods for placing programmable impedance memory elements in high impedance states 有权将可编程阻抗存储器元件置于高阻态中的电路和方法公开(公告)号：US09368198B1
公开(公告)日：2016-06-14
申请号：US14281830
申请日：2014-05-19
CPC分类号： G11C13/0011 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0073
摘要： A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
摘要翻译： 存储器件可以包括多个两端导电桥接随机存取存储器（CBRAM）型存储器元件; 至少一个程序晶体管被配置为响应于在其控制端处应用程序信号而使程序电流流过至少一个存储器元件，并且将程序偏置电压提供给存储器元件; 以及擦除负载电路，其包括至少一个二端二极管状负载元件，所述擦除负载电路被配置为使得擦除电流能够以与所述程序相反的方向流过所述负载元件和至少一个存储元件 当前。
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公开(公告)号：US06614283B1
公开(公告)日：2003-09-02
申请号：US10126564
申请日：2002-04-19
IPC分类号： H03L500
CPC分类号： H03K3/356113 , H03K17/102
摘要： In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.
摘要翻译： 在集成电路中，电压电平移位器将第一电压电平的输入信号转换为第二电压电平的输出信号。 电压电平移位器通常包括开关元件，例如晶体管，其控制逻辑零和逻辑一个值之间的输出信号的切换。 开关元件的最大电压低于它们可以工作的电压。 最大电压小于第二电压电平。 开关元件两端的电压被限制在小于最大电压。
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公开(公告)号：US20100281442A1
公开(公告)日：2010-11-04
申请号：US12432002
申请日：2009-04-29
IPC分类号： G06F17/50
CPC分类号： G01R31/31835
摘要： Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.
摘要翻译： 描述了与设备一起使用的设备（例如计算机系统或电路测试器），方法和计算机程序产品（即，软件）的实施例。 这些系统和过程可以用于统计学地表征集成电路中的子电路之间的相互依赖性（被称为“侵略者 - 受害者关系”）。 特别地，当集成电路针对一组状态变化差矢量失效时，侵略者和受害者之间的统计关系由性能度量（例如时钟速度）的值确定。 使用这些统计关系，选择状态变化差向量的最坏情况子组，例如最坏情况子组。 该子组可用于准确测试集成电路。
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公开(公告)号：US06864152B1
公开(公告)日：2005-03-08
申请号：US10442533
申请日：2003-05-20
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译： 通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。 第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。 浅沟和深沟的蚀刻然后同时进行。
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