In a DLL circuit of a DDR SDRAM, in addition to a replica buffer for compensating delay in an output buffer, a replica buffer for compensating flight time is provided. The phase of a clock signal CLKP outputted to the outside so as to be locked with a clock signal BUFFCLK can be adjusted in accordance with a control signal b[1:0]. For a controller receiving data in a lump from a plurality of semiconductor memory devices, the arriving timings of data from the semiconductor memory devices can be aligned. Therefore, it is unnecessary to capture data in response to a data strobe signal DQS, so that burden on the controller is lessened.