- 专利标题: Method of providing polysilicon spacer for implantation
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申请号: US10184520申请日: 2002-06-28
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公开(公告)号: US06573165B2公开(公告)日: 2003-06-03
- 发明人: PR Chidambaram
- 申请人: PR Chidambaram
- 主分类号: H01L21425
- IPC分类号: H01L21425
摘要:
An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than desired, implanting to form the source and drain of the PMOS transistor with dopant that moves faster during annealing such as Boron and then wet etching the polysilicon gates down to the shorter length such as the final length before implanting with the faster dopant such as arsenic.
公开/授权文献
- US20030008482A1 Method of providing polysilicon spacer for implantation 公开/授权日:2003-01-09
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