发明授权
US06576529B1 Method of forming an alignment feature in or on a multilayered semiconductor structure
有权
在多层半导体结构中或其上形成取向特征的方法
- 专利标题： Method of forming an alignment feature in or on a multilayered semiconductor structure
- 专利标题（中）： 在多层半导体结构中或其上形成取向特征的方法
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申请号： US09456224申请日： 1999-12-07
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公开(公告)号： US06576529B1公开(公告)日： 2003-06-10
- 发明人: David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
- 申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
- 主分类号： H01L23544
- IPC分类号： H01L23544
摘要：
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.