摘要:
A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要:
An electron beam lithographic apparatus has an electron gun providing a beam of accelerated electrons, a mask stage adapted to hold a mask in a path of the beam of accelerated electrons, and a workpiece stage adapted to hold a workpiece in a path of electrons that have passed through the mask. The electron gun has a cathode having an electron emission surface, an anode adapted to be connected to a high-voltage power supply to provide an electric field between the cathode and the anode to accelerate electrons emitted from the cathode toward the anode, and a current-density-profile control grid disposed between the anode and the cathode. The current-density-profile control grid is configured to provide an electron gun that produces an electron beam having a non-uniform current density profile. A method of producing a micro-device includes generating a beam of charged particles having a non-uniform charged-particle current density, illuminating a mask with the beam of charged particles, and exposing a workpiece with charged particles from the beam of charged particles.
摘要:
A process for device fabrication is disclosed. In the process, optical lithography is used to introduce an image of a desired pattern into an energy sensitive material. In the process, a filter element is provided. The filter element has at least two regions of different transmittance, each region denominated an aperture. The regions are selected by obtaining information about the desired pattern and an optical lithographic tool that will be used to introduce the image of the desired pattern into the energy sensitive resist material. A filter element that provides an image that, when developed, will provide features with dimensions within acceptable process tolerances is then designed. The filter element is designed by modeling the effects of each aperture of the filter element on the intensity profile of an image of the desired pattern. The combined effect of the apertures is then determined. If required, an aspect (transmittance, orientation, dimension) of the one or more of the proposed apertures is adjusted to provide a modeled intensity profile that more closely corresponds to the desired lithographic result. Once the aspects of all apertures is determined, the filter element is fabricated and used in the optical lithographic process by placing the filter element in the optical lithography tool.
摘要:
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要:
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要:
The present invention is directed to a lithographic process for device fabrication. In lithographic processes for device fabrication, exposing radiation is used to delineate the image of a pattern into a layer of an energy sensitive resist material formed over a substrate. The pattern is then developed and the pattern is introduced into the underlying substrate. In the present invention, the substrate, typically a silicon wafer, is placed in a tool which utilizes electron beams as the exposing radiation. The silicon wafer has topographic alignment marks formed thereon. The alignment marks are used to orient the wafer in the tool accurately. The placement of the wafer in the tool is monitored by observing the intensity of the electron signal backscattered from the surface of the substrate. The alignment mark configuration is selected to provide a desired contrast between the intensity of the backscattered electron signal in the aligned state and the intensity of backscattered electron signal in the non-aligned state. The alignment mark dimensions that provide the desired contrast for a given intensity of incident electrons are selected by determining a relationship between backscattered electron signal contrast as a function of a dimensionless parameter that is the ratio of an alignment mark dimension (h) to the range (R) of the scattered electrons in the substrate. From this relationship, the desired backscattered electron signal contrast is selected. The value of the dimensionless parameter that corresponds to this data point is then used to determine the alignment mark dimension that will provide the desired backscattered electron signal contrast.