A method of manufacturing semiconductor device having a structure in which the potential of a gate interconnection is not affected by that of a bit line when a dummy pad contact is formed at an end portion of a memory cell, in which no steps are formed in the vicinity of a memory cell end are obtained. The semiconductor device includes dummy pad contacts arranged in a dotted line, which are smaller than a first pad contact in the memory cell body and are opened using a self-alignment method, and a conduction is cut-off in a path leading from the dummy pad contact to the bit line.