发明授权
US06583000B1 Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation
失效
STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合
- 专利标题: Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation
- 专利标题(中): STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合
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申请号: US10072183申请日: 2002-02-07
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公开(公告)号: US06583000B1公开(公告)日: 2003-06-24
- 发明人: Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
- 申请人: Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
- 主分类号: H01L218238
- IPC分类号: H01L218238
摘要:
A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.