- 专利标题: Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve
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申请号: US09775711申请日: 2001-02-05
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公开(公告)号: US06590511B2公开(公告)日: 2003-07-08
- 发明人: Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
- 申请人: Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
- 优先权: JP2000-265078 20000901
- 主分类号: H03M700
- IPC分类号: H03M700
摘要:
A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.
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