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    Semiconductor memory device suitable for merging with logic
    2.
    发明授权
    Semiconductor memory device suitable for merging with logic 失效
    半导体存储器件适用于与逻辑电路合并

    公开(公告)号：US06418067B1

    公开(公告)日：2002-07-09

    申请号：US09592454

    申请日：2000-06-09

    申请人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    发明人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    IPC分类号： G11C700

    CPC分类号： G11C29/78 ,  G11C11/4076 ,  G11C29/846

    摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

    摘要翻译： 读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。 通过替换数据线对执行备用位修复。 列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。 提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。

    Low-power consumption semiconductor memory device
    4.
    发明申请
    Low-power consumption semiconductor memory device 失效
    低功耗半导体存储器件

    公开(公告)号：US20050041514A1

    公开(公告)日：2005-02-24

    申请号：US10949365

    申请日：2004-09-27

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C11/405 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    摘要翻译： 存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。 在选择状态下，第一和第二存储元件分别连接到互补位线。 在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。 可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

    Low-power consumption semiconductor memory device
    6.
    发明授权
    Low-power consumption semiconductor memory device 失效
    低功耗半导体存储器件

    公开(公告)号：US06804164B2

    公开(公告)日：2004-10-12

    申请号：US10437281

    申请日：2003-05-14

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C700

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    摘要翻译： 存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。 在选择状态下，第一和第二存储元件分别连接到互补位线。 在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。 可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。