发明授权
US06591393B1 Masking error detection/correction latency in multilevel cache transfers
有权
多级缓存传输中的掩码错误检测/校正延迟
- 专利标题: Masking error detection/correction latency in multilevel cache transfers
- 专利标题(中): 多级缓存传输中的掩码错误检测/校正延迟
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申请号: US09507208申请日: 2000-02-18
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公开(公告)号: US06591393B1公开(公告)日: 2003-07-08
- 发明人: Shawn Kenneth Walker , Dean A. Mulla , Donald Charles Soltis, Jr. , Terry L Lyon
- 申请人: Shawn Kenneth Walker , Dean A. Mulla , Donald Charles Soltis, Jr. , Terry L Lyon
- 主分类号: G11C2900
- IPC分类号: G11C2900
摘要:
Methods and apparatus mask the latency of error detection and/or error correction applied to data transferred between a first memory and a second memory. The method comprises determining whether there is an error in a data unit in the first memory; transferring data based on the data unit from the first memory to a second memory, wherein the transferring step commences before completion of the determining step; and disabling at least part of the second memory if the determining step detects an error in the data unit. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory.
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