公开(公告)号：US06728823B1

公开(公告)日：2004-04-27

申请号：US09507203

申请日：2000-02-18

申请人： Shawn Kenneth Walker ,  Terry L Lyon ,  Blaine Stackhouse

发明人： Shawn Kenneth Walker ,  Terry L Lyon ,  Blaine Stackhouse

IPC分类号： G06F1314

CPC分类号： G06F12/0897 ,  G06F12/0888

摘要： A source cache transfers data to an intermediate cache along a data connection. The intermediate cache is provided between the source cache and a target, and includes a memory array. The source cache may also transfer data to the target along the data connection while bypassing the memory array of the intermediate cache.

摘要翻译： 源缓存将数据沿数据连接传输到中间缓存。 中间缓存在源缓存和目标之间提供，并且包括存储器阵列。 源缓存还可以沿着数据连接将数据传送到目标，同时绕过中间高速缓存的存储器阵列。

公开(公告)号：US06557078B1

公开(公告)日：2003-04-29

申请号：US09510283

申请日：2000-02-21

申请人： Dean A. Mulla ,  Terry L Lyon ,  Reid James Riedlinger ,  Thomas Grutkowski

发明人： Dean A. Mulla ,  Terry L Lyon ,  Reid James Riedlinger ,  Thomas Grutkowski

IPC分类号： G06F1300

CPC分类号： G06F12/0855 ,  G06F12/0851 ,  G06F12/1054

摘要： The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

摘要翻译： 本发明的高速缓存使用排队结构，其为多个访问提供无序高速缓存存储器访问支持，以及用于管理银行冲突和地址冲突的支持。 本发明的高速缓存可以支持每个时钟命中的四个数据访问，支持每个时钟丢失L1缓存的一个访问，并且每个时钟支持一个指令访问。 响应散布在流水线中，从而使队列中的冲突最小化。 不冲突的访问不被禁止，但冲突的冲突消除之后，冲突的访问将被阻止。 本发明的缓存在管道的退役阶段之后提供无序支持。

公开(公告)号：US06493812B1

公开(公告)日：2002-12-10

申请号：US09465722

申请日：1999-12-17

申请人： Terry L Lyon

发明人： Terry L Lyon

IPC分类号： G06F1210

CPC分类号： G06F12/1054 ,  G06F2212/652

摘要： A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address aliasing are provided through a physical address CAM, page size mask compares and a column copy tag function. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. Multiple page sizes are supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.

摘要翻译： 采用预先验证的高速缓存标签设计的计算机微架构包括支持虚拟地址混叠和多页大小的电路。 通过物理地址CAM，页面大小掩码比较和列复制标签功能提供对各种地址混叠的支持。 还支持地址别名，使别名行无效，使用具有相同页大小的TLB条目进行地址混叠，以及对不同大小的TLB条目进行地址混叠。 通过添加页面大小的掩码RAM和虚拟和物理地址RAM，可以对预先生效的缓存标签设计进行扩展，支持多页大小。

公开(公告)号：US06493792B1

公开(公告)日：2002-12-10

申请号：US09495155

申请日：2000-01-31

申请人： Stephen R. Undy ,  Terry L Lyon

发明人： Stephen R. Undy ,  Terry L Lyon

IPC分类号： G11C1500

CPC分类号： G11C15/00 ,  G06F12/1027

摘要： A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a “hit” signal if the selected bit is the same as the corresponding bit of the stored tag value. Storage means are employed for recording the results of the compare with the M hit signal.

摘要翻译： 提供用于识别存储在CAM中的多个多个位标签值的CAM，其具有用于将输入的测试值的每个比特与所有存储的标签值的对应比特进行比较的逻辑电路。 采用位选择来产生用于顺序输入到逻辑电路中的多个测试位。 逻辑电路将多个测试位与每个存储的标签值的相应位进行比较，如果所选择的位与所存储的标签值的相应位相同，则产生“命中”信号。 采用存储手段来记录与M命中信号进行比较的结果。

公开(公告)号：US4660198A

公开(公告)日：1987-04-21

申请号：US723386

申请日：1985-04-15

申请人： Terry L. Lyon

发明人： Terry L. Lyon

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/34 ,  G06F11/00

CPC分类号： G01R31/318566 ,  G06F11/34

摘要： A circuit means for detecting data errors in VLSI processing circuits at the earliest point such an error occurs in the processing stream or (in different modes) at any selected point therein, and for providing the prior operands and faulty (intermediate) output data together with an indication of what is wrong with the data. Described are registers and/or means for controlling the mode of the circuitry, error detection means (being, for example, parity check circuits), and an output means for providing the output in an organized way responsive to the controlling means and the output of the error detecton means. The method of using such a circuit is inherent in the disclosure.

摘要翻译： 一种电路装置，用于在最早的时刻检测VLSI处理电路中的数据错误，例如在处理流中发生错误，或在其中任何选定的点处（或以不同的模式）发生错误，并且用于将先前的操作数和故障（中间）输出数据连同 指出数据有什么问题。 描述了用于控制电路模式，错误检测装置（例如奇偶校验电路）的寄存器和/或装置，以及用于以有组织的方式响应于控制装置提供输出的输出装置和输出 错误检测是指。 使用这种电路的方法在本公开中是固有的。

公开(公告)号：US07788429B2

公开(公告)日：2010-08-31

申请号：US12110795

申请日：2008-04-28

申请人： Terry L. Lyon

发明人： Terry L. Lyon

IPC分类号： G06F13/00 ,  G06F15/16 ,  H04L12/42 ,  H04L12/28

CPC分类号： G06F13/4282 ,  G06F2213/0026

摘要： In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.

摘要翻译： 在用于在多个数据通信实体之间传送数据的数据通信系统中，数据从至少第一数据通信实体和第二数据通信实体同时发送到串行数据环上。 串行数据环的第一部分交叉耦合到串行数据环的第二部分，使得来自第一数据通信实体的数据避免与来自第二数据通信实体的数据冲突，从而在单个数据环上仿真正向和反向传输 单向串行环。

公开(公告)号：US20090268638A1

公开(公告)日：2009-10-29

申请号：US12110795

申请日：2008-04-28

申请人： Terry L. Lyon

发明人： Terry L. Lyon

IPC分类号： H04L12/28

CPC分类号： G06F13/4282 ,  G06F2213/0026

摘要： In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.

摘要翻译： 在用于在多个数据通信实体之间传送数据的数据通信系统中，数据从至少第一数据通信实体和第二数据通信实体同时发送到串行数据环上。 串行数据环的第一部分交叉耦合到串行数据环的第二部分，使得来自第一数据通信实体的数据避免与来自第二数据通信实体的数据冲突，从而在单个数据环上仿真正向和反向传输 单向串行环。

公开(公告)号：US06874077B2

公开(公告)日：2005-03-29

申请号：US10648405

申请日：2003-08-27

申请人： Terry L Lyon

发明人： Terry L Lyon

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1054 ,  G06F12/1027

摘要： In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

摘要翻译： 在计算机系统中，并行分布式功能后备缓冲器（TLB）包括小型，快速的TLB和第二较大但较慢的TLB。 两个TLB并行运行，小型TLB接收整数负载数据，大型TLB接收其他虚拟地址信息。 通过在两个TLB之间分配诸如加载和存储指令以及整数和浮点指令的功能，小型TLB可以以低延迟进行操作，并避免抖动和类似问题，而较大的TLB为存储器密集型操作提供高带宽。 该机制还提供了一种并行存储更新和无效机制，对于预先验证的缓存标签设计特别有用。

公开(公告)号：US06625714B1

公开(公告)日：2003-09-23

申请号：US09466494

申请日：1999-12-17

申请人： Terry L Lyon

发明人： Terry L Lyon

IPC分类号： G06F1210

CPC分类号： G06F12/1054 ,  G06F12/1027

摘要： In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.

摘要翻译： 在计算机系统中，并行分布式功能后备缓冲器（TLB）包括小型，快速的TLB和第二较大但较慢的TLB。 两个TLB并行运行，小型TLB接收整数负载数据，大型TLB接收其他虚拟地址信息。 通过在两个TLB之间分配诸如加载和存储指令以及整数和浮点指令的功能，小型TLB可以以低延迟进行操作，并避免抖动和类似问题，而较大的TLB为存储器密集型操作提供高带宽。 该机制还提供了一种并行存储更新和无效机制，对于预先验证的缓存标签设计特别有用。

公开(公告)号：US06427188B1

公开(公告)日：2002-07-30

申请号：US09501396

申请日：2000-02-09

申请人： Terry L Lyon ,  Eric R DeLano ,  Dean A. Mulla

发明人： Terry L Lyon ,  Eric R DeLano ,  Dean A. Mulla

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F12/0884 ,  G06F12/0897 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： A system and method are disclosed which determine in parallel for multiple levels of a multi-level cache whether any one of such multiple levels is capable of satisfying a memory access request. Tags for multiple levels of a multi-level cache are accessed in parallel to determine whether the address for a memory access request is contained within any of the multiple levels. For instance, in a preferred embodiment, the tags for the first level of cache and the tags for the second level of cache are accessed in parallel. Also, additional levels of cache tags up to N levels may be accessed in parallel with the first-level cache tags. Thus, by the end of the access of the first-level cache tags it is known whether a memory access request can be satisfied by the first-level, second-level, or any additional N-levels of cache that are accessed in parallel. Additionally, in a preferred embodiment, the multi-level cache is arranged such that the data array of a level of cache is accessed only if it is determined that such level of cache is capable of satisfying a received memory access request. Additionally, in a preferred embodiment the multi-level cache is partitioned into N ways of associativity, and only a single way of a data array is accessed to satisfy a memory access request, thereby preserving the remaining ways of a data array to save power and resources that may be accessed to satisfy other instructions.

摘要翻译： 公开了一种系统和方法，其并行地确定多级高速缓存的多个级别，无论这样的多个级别中的任何一个是否能够满足存储器访问请求。 并行访问多级高速缓存的多级别的标签，以确定存储器访问请求的地址是否包含在多个级别中的任一级内。 例如，在优选实施例中，并行地访问用于第一级高速缓存的标签和用于第二级高速缓存的标签。 此外，可以与第一级缓存标签并行访问高达N级的缓存标签的附加级别。 因此，通过第一级缓存标签的访问结束，已知存储器访问请求是否可以由并行访问的高级缓存的第一级，第二级或任何附加N级满足。 此外，在优选实施例中，多级缓存被布置成使得仅当确定这种级别的高速缓存能够满足所接收的存储器访问请求时才能访问高速缓存级的数据阵列。 此外，在优选实施例中，多级缓存被分为N个关联方式，并且仅访问数据阵列的单一方式以满足存储器访问请求，从而保留数据阵列的剩余方式以节省功率， 可以访问的资源以满足其他指令。