发明授权
US06598216B2 Method for enhancing a power bus in I/O regions of an ASIC device
失效
用于增强ASIC设备的I / O区域中的电力总线的方法
- 专利标题: Method for enhancing a power bus in I/O regions of an ASIC device
- 专利标题(中): 用于增强ASIC设备的I / O区域中的电力总线的方法
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申请号: US09924673申请日: 2001-08-08
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公开(公告)号: US06598216B2公开(公告)日: 2003-07-22
- 发明人: Francis Chan , Charles S. Chiu , Robert Charles Cusimano , Donald S. Kent , Gulsun Yasar
- 申请人: Francis Chan , Charles S. Chiu , Robert Charles Cusimano , Donald S. Kent , Gulsun Yasar
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
A method for enhancing power bus for I/O libraries in ASIC designs is disclosed. An I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. In a determination that the I/O assignment does not meet the predetermined power bus distribution requirements, a power enhancement cell is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.
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