公开(公告)号：US06598216B2

公开(公告)日：2003-07-22

申请号：US09924673

申请日：2001-08-08

申请人： Francis Chan ,  Charles S. Chiu ,  Robert Charles Cusimano ,  Donald S. Kent ,  Gulsun Yasar

发明人： Francis Chan ,  Charles S. Chiu ,  Robert Charles Cusimano ,  Donald S. Kent ,  Gulsun Yasar

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for enhancing power bus for I/O libraries in ASIC designs is disclosed. An I/O assignment for I/O circuits to be utilized in an ASIC design is initially generated. Each I/O circuit may obtain power from either a primary I/O power bus or a secondary I/O power bus. A determination is then made as to whether or not the I/O assignment meets certain predetermined power distribution requirements. In a determination that the I/O assignment does not meet the predetermined power bus distribution requirements, a power enhancement cell is added. The power enhancement circuit includes at least one metal line for connecting the primary I/O power bus to the secondary I/O power bus in order for the I/O assignment to meet the power bus distribution requirements.

摘要翻译： 公开了一种用于增强ASIC设计中的I / O库的电源总线的方法。 最初生成用于ASIC设计中的I / O电路的I / O分配。 每个I / O电路可以从主I / O电源总线或辅助I / O电源总线获得电源。 然后确定I / O分配是否满足某些预定的功率分配要求。 在确定I / O分配不满足预定功率总线分配要求的情况下，增加功率增强单元。 功率增强电路包括用于将主I / O电源总线连接到辅助I / O电源总线的至少一个金属线，以便I / O分配满足电力总线分配要求。