- 专利标题： Monitoring and test structures for silicon etching
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申请号： US09917067申请日： 2001-07-26
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公开(公告)号： US06599761B2公开(公告)日： 2003-07-29
- 发明人: Jeffery S. Hess , Steven D. Leith , Donald W. Schulte , William Edwards , Jeffrey S. Obert , Timothy R. Emery
- 申请人： Jeffery S. Hess , Steven D. Leith , Donald W. Schulte , William Edwards , Jeffrey S. Obert , Timothy R. Emery
- 主分类号： H01L2100
- IPC分类号： H01L2100
摘要：
A through-substrate etching process is monitored by providing a sacrificial electrode in proximity to a desired etch window on the substrate. An etch process is performed on the substrate. The etch process is monitored by measuring an electrical property of either the substrate or the sacrificial electrode or both.
公开/授权文献
- US20030022397A1 Monitoring and test structures for silicon etching 公开/授权日：2003-01-30
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