发明授权
- 专利标题： Method to partition the physical design of an integrated circuit for electrical simulation
- 专利标题（中）： 分割用于电气仿真的集成电路的物理设计的方法
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申请号： US09371202申请日： 1999-08-10
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公开(公告)号： US06601025B1公开(公告)日： 2003-07-29
- 发明人: Gary S. Ditlow , Daria R. Dooling , Richard L. Moore , David E. Moran , Thomas W. Wilkins , Ralph J. Williams
- 申请人： Gary S. Ditlow , Daria R. Dooling , Richard L. Moore , David E. Moran , Thomas W. Wilkins , Ralph J. Williams
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.
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