公开(公告)号：US20080195989A1

公开(公告)日：2008-08-14

申请号：US12101599

申请日：2008-04-11

申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

IPC分类号： G06F9/45

CPC分类号： G06F17/5045

摘要： An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

摘要翻译： 一种用于预测VLSI设计产量的集成电路和程序产品。 提供一种集成电路，包括用于通过电路类型识别和分组集成电路设计中包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

公开(公告)号：US07434185B2

公开(公告)日：2008-10-07

申请号：US11535789

申请日：2006-09-27

申请人： Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

发明人： Daria R. Dooling ,  Kenneth T. Settlemyer, Jr. ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

摘要翻译： 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。

公开(公告)号：US06788302B1

公开(公告)日：2004-09-07

申请号：US09631764

申请日：2000-08-03

申请人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

发明人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

IPC分类号： G06F1580

CPC分类号： G06F9/5066

摘要： The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

摘要翻译： 本发明将大图形文件分割成更小的“帧”图形文件。 分割过程优选地在任意数量的处理器之间进行负载平衡。 这允许并行使用许多处理器来划分大图形文件，然后处理较小的输出帧。 此外，负载平衡以这样的方式执行，即只有图形文件的一部分需要被任何一个处理器加载。 这样可以节省内存和计算需求。 优选地，图形文件以三维方式分割，使得任何一个处理器将被分配一个三维块或图形文件的体积。 图形文件的三维分区将成为一帧，一个处理器访问图形文件，将其三维分区复制到新的输出帧中。

公开(公告)号：US07389480B2

公开(公告)日：2008-06-17

申请号：US10908342

申请日：2005-05-09

申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

摘要翻译： 一种用于预测VLSI设计产量的系统，方法和程序产品。 提供了一种方法，包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

公开(公告)号：US07315305B2

公开(公告)日：2008-01-01

申请号：US09224696

申请日：1999-01-04

申请人： Cassondra L. Crotty ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

发明人： Cassondra L. Crotty ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

IPC分类号： G06T11/20 ,  G09G5/00

CPC分类号： G06F17/5036

摘要： A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

摘要翻译： 用于可视化数据的系统和方法。 数据以数据数组的数据值或几何表示的形式提供。 数据阵列可以是例如稀疏矩阵。 几何表示可以是例如用几何描述语言编码的集成电路布局。 以数据值形式提供的数据与放置在网格上的几何形状相关联。 网格上的信息随后会报告给用户。 如果以几何表示的形式提供数据，则从几何表示中提取数据值。 从提取的数据值生成图形表示。 图形表示呈现给用户。

公开(公告)号：US06301690B1

公开(公告)日：2001-10-09

申请号：US09294495

申请日：1999-07-12

申请人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Richard L. Moore ,  Gustavo E. Tellez ,  Ralph J. Williams ,  Thomas W. Wilkins

发明人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Richard L. Moore ,  Gustavo E. Tellez ,  Ralph J. Williams ,  Thomas W. Wilkins

IPC分类号： G06F1750

CPC分类号： H01L22/20 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.

摘要翻译： 一种具有改善的缺陷限制产量的集成电路的制造方法。 集成电路上的每个导体被表示为具有分支电压和电流的网络的电气元件。 有利地，导体的宽度选择为具有产生具有足够噪声容限的信号电平所需的最小宽度。 因此，实现了沿着各种导体元件长度的一部分具有减小的横截面面积的集成电路导电栅格，以减少在制造期间产生的颗粒将导致相邻导体元件的桥接的风险。

公开(公告)号：US07051307B2

公开(公告)日：2006-05-23

申请号：US10707286

申请日：2003-12-03

申请人： Gary S. Ditlow ,  Daria R. Dooling ,  Timothy G. Dunham ,  William C. Leipold ,  Stephen D. Thomas ,  Ralph J. Williams

发明人： Gary S. Ditlow ,  Daria R. Dooling ,  Timothy G. Dunham ,  William C. Leipold ,  Stephen D. Thomas ,  Ralph J. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

摘要翻译： 公开了通过基于设计层级中的逻辑宏的大小启发式来识别集成电路设计中的逻辑块来分割集成电路设计的方法和结构。 本发明确定逻辑块的数量是否在期望数量的逻辑块的范围内，并重复识别用于集成电路设计的不同层级的逻辑块的处理，直到逻辑块的数量在所需数量的范围内 的逻辑块。 这作为分配芯片的指南，而不是格栅分割。

公开(公告)号：US06601025B1

公开(公告)日：2003-07-29

申请号：US09371202

申请日：1999-08-10

申请人： Gary S. Ditlow ,  Daria R. Dooling ,  Richard L. Moore ,  David E. Moran ,  Thomas W. Wilkins ,  Ralph J. Williams

发明人： Gary S. Ditlow ,  Daria R. Dooling ,  Richard L. Moore ,  David E. Moran ,  Thomas W. Wilkins ,  Ralph J. Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.

摘要翻译： 提供了一种用于设计集成电路的方法，该集成电路包括接收集成电路的图形描述，从集成电路的图形描述中提取与特定电路功能有关的形状，以及将提取的形状分割成多个段。 该方法可以形成多个段中的每一个的集成电路的电表示，并且基于电表示求解多个段中的每一个的矩阵方程（Gv = i）。

公开(公告)号：US07661081B2

公开(公告)日：2010-02-09

申请号：US12101599

申请日：2008-04-11

申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

摘要翻译： 一种用于预测VLSI设计产量的集成电路系统和程序产品。 提供一种集成电路系统，包括用于通过电路类型识别和集成集成电路设计中所包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

公开(公告)号：US20080077891A1

公开(公告)日：2008-03-27

申请号：US11535789

申请日：2006-09-27

申请人： Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

发明人： Daria R. Dooling ,  Kenneth T. Settlemyer ,  Jacek G. Smolinski ,  Stephen D. Thomas ,  Ralph J. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

摘要翻译： 一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。 该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业 文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到 主机用于聚合处理。