发明授权
- 专利标题: Systems and methods for on-chip impedance termination
- 专利标题(中): 用于片上阻抗终止的系统和方法
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申请号: US10044459申请日: 2002-01-11
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公开(公告)号: US06603329B1公开(公告)日: 2003-08-05
- 发明人: Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
- 申请人: Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
- 主分类号: H03K1716
- IPC分类号: H03K1716
摘要:
Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.
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