公开(公告)号：US08593195B1

公开(公告)日：2013-11-26

申请号：US13614526

申请日：2012-09-13

申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

IPC分类号： H03H11/16

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

公开(公告)号：US20130120044A1

公开(公告)日：2013-05-16

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

摘要翻译： 提供了具有时钟发生和分配电路的集成电路。 集成电路可以包括被配置为生成作为彼此的延迟版本的多个时钟信号的锁相环。 时钟信号可以使用串行连接的时钟缓冲器块分布到集成电路上的各个区域。 每个缓冲块可以包括并联耦合的双向缓冲电路对。 每个缓冲电路可以具有被配置为接收输入时钟信号的第一输入，提供输入时钟信号的校正版本的输出（例如，提供具有期望的占空比的输出时钟信号的输出）， 第二输入端，接收用于设定所述输出时钟信号的期望占空比的第一延迟时钟信号;以及第三输入端，其接收至少当所述第一延迟时钟信号上升时为高的第二延迟时钟信号。

公开(公告)号：US08368449B1

公开(公告)日：2013-02-05

申请号：US13179495

申请日：2011-07-09

申请人： John Bui ,  Chiakang Sung ,  Khai Nguyen

发明人： John Bui ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03H11/16 ,  H03L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： A circuit includes a phase adjustment circuit and a dead zone detect circuit. The phase adjustment circuit is operable to receive periodic signals and is operable to provide one of the periodic signals as a selected periodic signal based on a phase comparison between a data signal and the selected periodic signal. Each of the periodic signals has a different phase. The dead zone detect circuit is operable to cause the phase adjustment circuit to shift a phase of the selected periodic signal if the dead zone detect circuit determines that the data signal is in a dead zone. The dead zone detect circuit defines the dead zone based on two of the periodic signals. The phase adjustment circuit is operable to adjust a phase range of the dead zone.

摘要翻译： 电路包括相位调整电路和死区检测电路。 相位调整电路可操作以接收周期性信号，并且可操作以基于数据信号与所选择的周期信号之间的相位比较，将周期信号之一提供为所选择的周期信号。 每个周期信号具有不同的相位。 如果死区检测电路确定数据信号处于死区，则死区检测电路可操作以使相位调整电路移位所选周期信号的相位。 死区检测电路基于两个周期信号定义死区。 相位调整电路可操作以调节死区的相位范围。

公开(公告)号：US20120311277A1

公开(公告)日：2012-12-06

申请号：US13151101

申请日：2011-06-01

申请人： Michael H.M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

发明人： Michael H.M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

IPC分类号： G06F12/08

CPC分类号： G06F13/1626 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/18

摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.

摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控​​制器。 存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。 为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。 优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。 优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。

公开(公告)号：US08237475B1

公开(公告)日：2012-08-07

申请号：US12248031

申请日：2008-10-08

申请人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

发明人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

IPC分类号： H03L7/06

CPC分类号： H03L7/0805 ,  H03L7/0814 ,  H03L7/0816

摘要： A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

摘要翻译： 电路包括锁定环和相位偏移电路。 锁定环产生用于控制锁定环路中的第一延迟的第一控制信号。 相位偏移电路延迟由第二控制信号控制的第二延迟的输入信号以产生延迟的信号。 相位偏移电路通过调整第一控制信号来产生第二控制信号，以提高相对于目标相位的延迟信号的精度。 第二控制信号补偿由电路的过程，电源电压和温度中的至少一个的变化引起的第二延迟的变化的至少一部分。

公开(公告)号：US08130016B2

公开(公告)日：2012-03-06

申请号：US12642502

申请日：2009-12-18

申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 每个可变延迟块和固定延迟块都是反相的。

公开(公告)号：US20110175657A1

公开(公告)日：2011-07-21

申请号：US12690064

申请日：2010-01-19

申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：US07710149B1

公开(公告)日：2010-05-04

申请号：US12190530

申请日：2008-08-12

申请人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

发明人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

IPC分类号： H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/018585

摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

摘要翻译： 输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。 例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。 一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

公开(公告)号：US07671579B1

公开(公告)日：2010-03-02

申请号：US11470898

申请日：2006-09-07

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： G01R23/175 ,  G08B23/00

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07590879B1

公开(公告)日：2009-09-15

申请号：US11043524

申请日：2005-01-24

申请人： Henry Kim ,  Bonnie I. Wang ,  ChiaKang Sung ,  Joseph Huang

发明人： Henry Kim ,  Bonnie I. Wang ,  ChiaKang Sung ,  Joseph Huang

IPC分类号： G06F1/12 ,  G06F9/00 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.

摘要翻译： 用于对时钟信号的上升沿和下降沿进行偏移的电路，方法和装置。 本发明的一个实施例利用数据路径中的延迟元件来调整数据信号，使得时钟信号相对于数据居中。 本发明的另一实施例使用两个触发器来恢复双数据速率信号，其中一个触发器由时钟上升沿计时，另一个由时钟下降沿计时。 在一个或两个触发器时钟输入的前面插入一个附加的延迟元件。 如果使用两个额外的延迟元件，则它们可独立调节，以便可以独立调整每个边沿以改善数据恢复。