发明授权
US06608744B1 SOI CMOS input protection circuit with open-drain configuration
有权
SOI CMOS输入保护电路，具有开漏配置
- 专利标题： SOI CMOS input protection circuit with open-drain configuration
- 专利标题（中）： SOI CMOS输入保护电路，具有开漏配置
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申请号： US09432102申请日： 1999-11-02
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公开(公告)号： US06608744B1公开(公告)日： 2003-08-19
- 发明人: Katsuhiro Kato
- 申请人： Katsuhiro Kato
- 主分类号： H02H322
- IPC分类号： H02H322
摘要：
An integrated circuit fabricated by silicon-on-insulator technology has an input terminal coupled to the gate electrodes of a CMOS inverter. Within the integrated circuit, the input terminal is coupled through a first protective element either to the power supply or to ground, but not to both. A second protective element is coupled in parallel with the inverter between the power supply and ground. This configuration protects both transistors in the inverter from input surges, without restricting the normal input voltage to the range between the power-supply voltage and ground.
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