公开(公告)号：US06775121B1

公开(公告)日：2004-08-10

申请号：US10216367

申请日：2002-08-09

申请人： Nisar A. Chaudhry

发明人： Nisar A. Chaudhry

IPC分类号： H02H322

CPC分类号： H04M3/18 ,  H02H9/042 ,  H02H9/06

摘要： Power line surge protection device comprising AC power line overvoltage protection, telephone voice line overvoltage and overcurrent protection, high speed data line overvoltage and overcurrent protection, coaxial transmission line overvoltage protection, and a ground-sensing indicator, all tied to a common ground.

摘要翻译： 电力线浪涌保护装置包括交流电源线过电压保护，电话语音线路过压和过流保护，高速数据线过压和过流保护，同轴传输线过电压保护和地线传感指示器，均与公共地线相连。

公开(公告)号：US06768618B1

公开(公告)日：2004-07-27

申请号：US10210279

申请日：2002-08-01

申请人： Sanjeev Kumar Maheshwari ,  Roger Jay Bettman

发明人： Sanjeev Kumar Maheshwari ,  Roger Jay Bettman

IPC分类号： H02H322

CPC分类号： H03K19/00315

摘要： An input gate protection circuit has a pass transistor having a source coupled to an input signal. A first voltage range control circuit is coupled to a gate of the pass transistor. A second voltage range is control circuit coupled to the gate of the pass transistor.

摘要翻译： 输入栅极保护电路具有耦合到输入信号的源极的通过晶体管。 第一电压范围控制电路耦合到传输晶体管的栅极。 第二电压范围是耦合到传输晶体管的栅极的控制电路。

公开(公告)号：US06636404B1

公开(公告)日：2003-10-21

申请号：US09649762

申请日：2000-08-28

申请人： Stephen J. Whitney ,  David Zhang ,  Scott Davidson

发明人： Stephen J. Whitney ,  David Zhang ,  Scott Davidson

IPC分类号： H02H322

CPC分类号： H01C7/12 ,  H01C7/13

摘要： An integrated overvoltage and overcurrent circuit protection device for use in telecommunication circuits. The integrated circuit protection device combines a overcurrent device such as a fuse and a overvoltage protection device such as a thyristor to respectively protect against overcurrent conditions and transient overvoltages. Integration of multiple devices in a common package ensures proper coordination and matching of the components, reduces the final product cost and reduces the physical space required on a telecommunications circuit for overvoltage and overcurrent circuit protection.

摘要翻译： 一种用于通信电路的集成过电压和过流电路保护装置。 集成电路保护装置组合了诸如熔断器的过电流装置和诸如晶闸管的过电压保护装置，以分别防止过电流状况和瞬态过电压。 将多个设备集成在通用包中可确保组件的正确协调和匹配，降低最终产品成本，并减少电信电路所需的物理空间，以实现过电压和过流电路保护。

公开(公告)号：US06487060B1

公开(公告)日：2002-11-26

申请号：US09916382

申请日：2001-07-27

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： H02H322

CPC分类号： G11C5/145

摘要： A protection system that protects a booster circuit used to boost operating signals in a memory device. The system includes a protection circuit for protecting an output transistor of the booster circuit. The protection circuit includes a transfer gate coupled to the output transistor and coupled to receive a first boost signal and a second boost signal. The transfer gate opens and closes in response to the second boost signal. When the transfer gate is closed, the first boost signal is uncoupled from the output transistor, and when the transfer gate is opened, the first boost signal is coupled to the output transistor. The circuit also includes a protection transistor coupled to the second boost signal, a supply voltage and the output transistor, where the protection transistor couples the supply voltage to the output transistor when the transfer gate is closed.

摘要翻译： 保护系统，其保护用于升高存储器件中的操作信号的升压电路。 该系统包括用于保护升压电路的输出晶体管的保护电路。 保护电路包括耦合到输出晶体管并被耦合以接收第一升压信号和第二升压信号的传输栅极。 转移门响应于第二升压信号而打开和关闭。 当传输门关闭时，第一升压信号与输出晶体管分离，当传输门断开时，第一升压信号耦合到输出晶体管。 电路还包括耦合到第二升压信号的保护晶体管，电源电压和输出晶体管，其中当传输门关闭时，保护晶体管将电源电压耦合到输出晶体管。

公开(公告)号：US06469884B1

公开(公告)日：2002-10-22

申请号：US09472710

申请日：1999-12-24

申请人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

发明人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

IPC分类号： H02H322

CPC分类号： G11C17/18

摘要： An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

摘要翻译： 具有至少一个可编程熔丝（F1）和ESD电路（MN3，MN1）的集成电路（10）防止当在主电压电位（Vmain）上存在电压瞬变时熔丝（F1）被无意地烧断。 ESD电路优选地包括MOSFET开关，其由于电压瞬变而被耦合以比主熔丝编程开关（MNmain）更快地接通，从而确保主开关在电压瞬变期间保持关断以防止熔丝的无意的吹动 F1。 该电路非常适用于可编程逻辑器件（PLD），允许低至6伏的读取电压，并允许高达40伏的编程电压。

公开(公告)号：US06385021B1

公开(公告)日：2002-05-07

申请号：US09546601

申请日：2000-04-10

申请人： Fujio Takeda ,  James W. Miller

发明人： Fujio Takeda ,  James W. Miller

IPC分类号： H02H322

CPC分类号： H01L27/0248 ,  H01L27/0266

摘要： An ESD protection circuit (39) coupled to each of a plurality of I/O circuits (30, 32, 36) of an integrated circuit (31) is disclosed. The ESD protection circuit includes a MOSFET transistor (40) to provide primary ESD protection on occurrence of an ESD event. In one embodiment, the control electrode of the MOSFET transistor is coupled to a first buffer circuit (42). Integrated circuit (31) includes a remote trigger circuit (37) coupled to the ESD protection circuits via a trigger bus (47). The individual ESD protection circuits operate in parallel to provide ESD protection to the I/O circuits (30, 32, and 36) upon occurrence of an ESD event.

摘要翻译： 公开了一种耦合到集成电路（31）的多个I / O电路（30,32,36）中的每一个的ESD保护电路（39）。 ESD保护电路包括MOSFET晶体管（40），用于在发生ESD事件时提供主要的ESD保护。 在一个实施例中，MOSFET晶体管的控制电极耦合到第一缓冲电路（42）。 集成电路（31）包括经由触发总线（47）耦合到ESD保护电路的远程触发电路（37）。 各个ESD保护电路并联工作，以在ESD事件发生时向I / O电路（30,32和36）提供ESD保护。

公开(公告)号：US06351363B1

公开(公告)日：2002-02-26

申请号：US09328849

申请日：1999-06-09

申请人： Tai-Ho Wang

发明人： Tai-Ho Wang

IPC分类号： H02H322

CPC分类号： H01L27/0255 ,  H02H9/046

摘要： A multi-stage polydiode-based electrostatic discharge (ESD) protection circuit is provided for use in an IC device to protect the internal circuit of the IC device against ESD. In use, the multi-stage polydiode-based ESD protection circuit of the invention is provided between a bonding pad and the internal circuit of the IC device for the purpose of protecting the internal circuit of the IC device against any ESD voltage applied to the bonding pad. The multi-stage polydiode-based ESD protection circuit of the invention comprises: a plurality of stages of polydiode circuits; a plurality of resistors, each being connected between two neighboring stages of the polydiode circuits; and a power protection circuit connected between a high system voltage line and a low system voltage line. When ESD occurs, the resulted ESD current will be diverted by the polydiode circuits to the high system voltage line, and subsequently diverted by the power protection circuit to the low system voltage line, thus preventing the ESD current from entering into the internal circuit of the IC device. Moreover, with silicon dioxide layer serving as isolation between the polydiode structure and the underlying substrate, the ESD current is also presented from flowing to the substrate. The multi-stage polydiode-based ESD protection circuit thus can help provide adequate ESD protection against various types of ESD, including HBM (Human-Body Model), MM (Machine Model), and CDM (Charge-Device Model).

摘要翻译： 提供了一种用于IC器件的多级多晶硅基静电放电（ESD）保护电路，以保护IC器件的内部电路免受ESD。 在使用中，本发明的多级多极体系ESD保护电路设置在接合焊盘与IC器件的内部电路之间，用于保护IC器件的内部电路免受施加于接合的任何ESD电压 垫。 本发明的基于多级多极体的ESD保护电路包括：多级多极电路; 多个电阻器，各自连接在所述多极电路的两个相邻级之间; 以及连接在高系统电压线和低系统电压线之间的电源保护电路。 当ESD发生时，所产生的ESD电流将被多晶硅电路转移到高系统电压线，并随后由电源保护电路转移到低系统电压线，从而防止ESD电流进入内部电路 IC设备。 此外，由于二氧化硅层用作多晶硅结构和下层衬底之间的隔离，ESD电流也呈现流向衬底。 因此，基于多级多极体的ESD保护电路可以帮助提供足够的ESD保护，以防止各种类型的ESD，包括HBM（人体模型），MM（机器模型）和CDM（充电器件模型）。

公开(公告)号：US06288885B1

公开(公告)日：2001-09-11

申请号：US09388521

申请日：1999-09-02

申请人： Tongbi Jiang ,  David Y. Kao

发明人： Tongbi Jiang ,  David Y. Kao

IPC分类号： H02H322

CPC分类号： H01L23/60 ,  H01L27/0248 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K1/0254 ,  H01L2924/00 ,  H01L2224/05599

摘要： An in its various embodiments is a method and apparatus for electrostatic discharge protection. In one aspect of the present invention, an integrated circuit device capable of providing electrostatic discharge protection for use on a printed circuit board containing a possible source of electrostatic discharge and operational circuitry is provided. The integrated circuit device includes an input coupled to the possible source of electrostatic discharge, an output coupled to the operational circuitry on the printed circuit board, a capacitance structure between the input and the output, and a switch in series with the capacitance structure. The integrated circuit also provides, a method for protecting a printed circuit board from electrostatic discharge by switching the discharge to a capacitance structure for subsequent dissipation into the printed circuit board.

摘要翻译： 其各种实施例中的静电放电保护的方法和装置。 在本发明的一个方面，提供一种能够提供静电放电保护以用于包含可能的静电放电源和操作电路的印刷电路板的集成电路器件。 集成电路器件包括耦合到可能的静电放电源的输入，耦合到印刷电路板上的操作电路的输出，输入和输出之间的电容结构以及与电容结构串联的开关。 集成电路还提供了一种通过将放电切换到电容结构以便随后耗散到印刷电路板中来保护印刷电路板免受静电放电的方法。

公开(公告)号：US06268993B1

公开(公告)日：2001-07-31

申请号：US09349269

申请日：1999-07-07

申请人： Warren R. Anderson

发明人： Warren R. Anderson

IPC分类号： H02H322

CPC分类号： H01L27/0266 ,  H02H9/046

摘要： An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The technique uses an ESD protection circuit that includes a two cascode-connected clamps between the protected pad and a reference voltage conductor and an level-shifting inverter amplifier for driving the clamps. A control signal used to control the amplifiers is derived from a nominal-voltage pad, but the voltage used to activate the transistor clamps is derived from the protected pad to achieve the greatest voltage drive on the cascoded clamps during ESD.

摘要翻译： 静电放电（ESD）保护技术保护半导体器件免受静电放电事件的影响。 该技术使用ESD保护电路，其在受保护的焊盘和参考电压导体之间包括两个共源共栅连接的钳位，以及用于驱动钳位的电平移位反相放大器。 用于控制放大器的控制信号来自标称电压焊盘，但是用于激活晶体管钳位电压的电压是从受保护的焊盘导出的，以在ESD期间在级联夹具上实现最大的电压驱动。

公开(公告)号：US06249413B1

公开(公告)日：2001-06-19

申请号：US09314982

申请日：1999-05-20

申请人： Charvaka Duvvury

发明人： Charvaka Duvvury

IPC分类号： H02H322

CPC分类号： H01L27/0266

摘要： Protection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14).

摘要翻译： 提供了用于保护集成电路免受ESD脉冲的保护电路（10）。 保护电路（10）包括在衬底（11）上的放电电路（14），其将ESD脉冲放电到集成电路到地（18）。 保护电路（10）还包括使用ESD脉冲能量的一部分来偏置放电电路（14）的衬底（11）的衬底偏置发生器（25）。