发明授权
- 专利标题: Memory circuit for preventing rise of cell array power source
- 专利标题(中): 用于防止电池阵列电源上升的存储电路
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申请号: US09776909申请日: 2001-02-06
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公开(公告)号: US06611472B2公开(公告)日: 2003-08-26
- 发明人: Ayako Kitamoto , Kaoru Mori
- 申请人: Ayako Kitamoto , Kaoru Mori
- 优先权: JP2000-038874 20000216
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
The present invention is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.
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