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    METHOD FOR CULTURING CELLS IN A SYSTEM COMPRISING LAMININ-5
    3.
    发明申请
    METHOD FOR CULTURING CELLS IN A SYSTEM COMPRISING LAMININ-5 审中-公开
    在包含LAMININ-5的系统中培养细胞的方法

    公开(公告)号：US20130164839A1

    公开(公告)日：2013-06-27

    申请号：US13638172

    申请日：2011-03-31

    申请人： Hisataka Yasuda ,  Munehiro Yamada ,  Yukiko Taketani ,  Yoshiya Tomimori ,  Kaoru Mori

    发明人： Hisataka Yasuda ,  Munehiro Yamada ,  Yukiko Taketani ,  Yoshiya Tomimori ,  Kaoru Mori

    IPC分类号： C12N5/071 ,  C12N5/0735 ,  C12N5/0775 ,  C12N5/0786 ,  C12N5/0797 ,  C12N5/077 ,  C12N5/078 ,  C12N5/09 ,  C12N5/0789

    CPC分类号： C07K14/78 ,  C12N5/0068 ,  C12N2533/52

    摘要： The present invention is directed to providing a method for culturing cells in a system containing laminin-5. The method of the present invention is characterized by a culture system containing a polypeptide selected from a group consisting of: a protein in blood other than extracellular matrix proteins, which is, serum, serum albumin, prealbumin, immunoglobulin, α-globulin, β-globulin, α1-antitrypsin (α1-AT), heptoglobin (Hp), α2-macroglobulin (α2-M), α-fetoprotein (AFP), transferrin, retinol-binding protein (RBP) or adiponectin; gelatin; a protein belonging to a tumor necrosis factor (TNF) family; and peptone.

    摘要翻译： 本发明旨在提供一种在含有层粘连蛋白-5的系统中培养细胞的方法。 本发明的方法的特征在于包含选自以下的多肽的培养系统：除了细胞外基质蛋白之外的血液中的蛋白质，即血清，血清白蛋白，前白蛋白，免疫球蛋白，α-球蛋白，β- 球蛋白，α1-抗胰蛋白酶（α1-AT），肝球蛋白（Hp），α2-巨球蛋白（α2-M），甲胎蛋白（AFP），转铁蛋白，视黄醇结合蛋白（RBP）或脂联素; 明胶; 属于肿瘤坏死因子（TNF）家族的蛋白质; 和蛋白胨。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08111575B2

    公开(公告)日：2012-02-07

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C5/14

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    Semiconductor memory and method for testing the same
    5.
    发明授权
    Semiconductor memory and method for testing the same 有权
    半导体存储器及其测试方法

    公开(公告)号：US07937630B2

    公开(公告)日：2011-05-03

    申请号：US11797699

    申请日：2007-05-07

    申请人： Kaoru Mori

    发明人： Kaoru Mori

    IPC分类号： G11C29/00

    CPC分类号： G11C29/16 ,  G11C2029/1804

    摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.

    摘要翻译： 一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。 多个CR保持操作模式信息。 当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息 时分基础。 响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。 另外，每当更新多个CR时，命令生成部重新生成测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据 数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100110818A1

    公开(公告)日：2010-05-06

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C7/00 ,  H03K17/00 ,  H03K17/56 ,  G11C8/00

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    Semiconductor memory, test method of semiconductor memory and system
    9.
    发明授权
    Semiconductor memory, test method of semiconductor memory and system 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US07672181B2

    公开(公告)日：2010-03-02

    申请号：US12130578

    申请日：2008-05-30

    申请人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

    发明人： Kaoru Mori ,  Kota Hara ,  Jun Ohno

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

    摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

    摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。

    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
    10.
    发明申请
    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US20090040851A1

    公开(公告)日：2009-02-12

    申请号：US12130578

    申请日：2008-05-30

    申请人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

    发明人： Kaoru MORI ,  Kota Hara ,  Jun Ohno

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/025 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2211/4061

    摘要： Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.

    摘要翻译： 每个子字线耦合到存储器单元的转移晶体管的栅极。 当主字线处于激活电平时，子字解码器的第一开关将子字线耦合到高电平电压线。 当主字线处于钝化级别时，第二开关将子字线耦合到低电平电压线。 当字复位信号线处于激活电平时，第三开关将子字线耦合到低电平电压线。 复位控制电路在测试模式期间禁用主字线的失活或字复位信号线的激活。 第二和第三开关中的一个被强制关闭，从而可以容易地检测到子字解码器的操作故障。