- 专利标题: Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
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申请号: US09805707申请日: 2001-03-14
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公开(公告)号: US06613652B2公开(公告)日: 2003-09-02
- 发明人: Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
- 申请人: Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
- 主分类号: H01L2130
- IPC分类号: H01L2130
摘要:
A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.
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