发明授权
- 专利标题: Process for fabricating secure integrated circuit
- 专利标题(中): 制造安全集成电路的过程
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申请号: US09607009申请日: 2000-06-29
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公开(公告)号: US06613661B1公开(公告)日: 2003-09-02
- 发明人: James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
- 申请人: James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
- 主分类号: H01L2144
- IPC分类号: H01L2144
摘要:
An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
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