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    INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS
    2.
    发明申请
    INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS 失效
    使用良好的植入物进行集成电路修改

    公开(公告)号：US20090170255A1

    公开(公告)日：2009-07-02

    申请号：US12399628

    申请日：2009-03-06

    申请人： Lap-Wai Chow ,  William M. Clark, JR. ,  James P. Baukus ,  Gavin J. Harbison

    发明人： Lap-Wai Chow ,  William M. Clark, JR. ,  James P. Baukus ,  Gavin J. Harbison

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823892 ,  H01L27/02

    摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

    摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。

    Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
    3.
    发明授权
    Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效
    永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管

    公开(公告)号：US06740942B2

    公开(公告)日：2004-05-25

    申请号：US09882892

    申请日：2001-06-15

    申请人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    发明人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    IPC分类号： H01L2976

    CPC分类号： H01L27/0203 ,  H01L21/76895 ,  H01L21/823462 ,  H01L23/576 ,  H01L27/0883 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

    摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

    摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。

    Building block for a secure CMOS logic cell library
    4.
    发明授权
    Building block for a secure CMOS logic cell library 有权
    用于安全CMOS逻辑单元库的构建块

    公开(公告)号：US08111089B2

    公开(公告)日：2012-02-07

    申请号：US12786205

    申请日：2010-05-24

    申请人： Ronald P. Cocchi ,  James P. Baukus ,  Bryan J. Wang ,  Lap Wai Chow ,  Paul Ouyang

    发明人： Ronald P. Cocchi ,  James P. Baukus ,  Bryan J. Wang ,  Lap Wai Chow ,  Paul Ouyang

    IPC分类号： H03K19/00 ,  H03K19/20 ,  H03K19/094

    CPC分类号： H03K19/20

    摘要： A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.

    摘要翻译： 公开了使用构建块来设计用于CMOS（互补金属氧化物硅）ASIC（专用集成电路）的逻辑单元库的逻辑构建块和方法。 具有与本发明中描述的相同构造块构建的不同逻辑门将具有与晶体管连接相同的原理图以及相同的物理布局，使得它们在光学或电子显微镜下似乎在物理上相同。 由这种逻辑单元的库设计的ASIC非常耐逆向工程尝试。

    Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same
    8.
    发明授权
    Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same 失效
    可编程连接器/隔离器和双层多晶硅层CMOS工艺与埋地接触使用相同

    公开(公告)号：US06893916B2

    公开(公告)日：2005-05-17

    申请号：US10619981

    申请日：2003-07-14

    申请人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    发明人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    IPC分类号： H01L21/768 ,  H01L27/02 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/00

    CPC分类号： H01L27/02 ,  H01L21/76895 ,  H01L23/573 ,  H01L27/0203

    摘要： An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity tape; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.

    摘要翻译： 一种用于包括第一导电类型的硅衬底的MOS器件的集成电路结构; 选择性地放置在第一导电带的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层; 选择性地放置在所述第一栅极绝缘区域和所述第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在所述第二栅极绝缘区域上的第二多晶硅层; 埋在第一导电类型的硅衬底内的第二导电类型的第一掩埋硅区域放置在第一多晶硅层下方并与其接触; 以及第二导电类型的第二掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第二栅极绝缘区域的下面，在第二多晶硅层下方并与其绝缘。

    Secure integrated circuit
    9.
    发明授权
    Secure integrated circuit 失效
    安全集成电路

    公开(公告)号：US06294816B1

    公开(公告)日：2001-09-25

    申请号：US09087748

    申请日：1998-05-29

    申请人： James P. Baukus ,  William M. Clark, Jr. ,  Lap-Wai Chow ,  Allan R. Kramer

    发明人： James P. Baukus ,  William M. Clark, Jr. ,  Lap-Wai Chow ,  Allan R. Kramer

    IPC分类号： H01L2976

    CPC分类号： H01L23/573 ,  G11C7/24 ,  H01L27/02 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.

    摘要翻译： 通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。 掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。 衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。