- 专利标题： Method for evaluating decoupling capacitor placement for VLSI chips
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申请号： US09896270申请日： 2001-06-29
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公开(公告)号： US06618844B2公开(公告)日： 2003-09-09
- 发明人: Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
- 申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
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