利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.016 秒)

    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
    1.
    发明授权
    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
    针对频率相关串扰模拟的三维互连结构建模的高效方法

    公开(公告)号：US06418401B1

    公开(公告)日：2002-07-09

    申请号：US09248667

    申请日：1999-02-11

    申请人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    发明人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

    摘要翻译： 一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。 该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。 这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。 快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

    Minimal length method for positioning unit pins in a hierarchically designed VLSI chip
    4.
    发明授权
    Minimal length method for positioning unit pins in a hierarchically designed VLSI chip 失效
    用于在分层设计的VLSI芯片中定位单元引脚的最小长度方法

    公开(公告)号：US06415428B1

    公开(公告)日：2002-07-02

    申请号：US09422287

    申请日：1999-10-21

    申请人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    发明人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.

    摘要翻译： 一种用于在不改变单元布置的情况下，将次优定位单元引脚识别和定位在分层设计的VSLI芯片中的方法，包括：生成平坦数据文件，使用包括用于单元引脚和宏引脚的数据的平面数据文件生成第一引脚日志 使用包括网的宏引脚的数据的平坦数据文件生成第二引脚对数，使用第一引脚对数确定最小净长度，并使用第二引脚对数确定最小净长度，计算第 使用第一引脚对数确定的最小净长度和使用第二引脚对数确定的最小净长度，通过将计算出的差异与阈值进行比较来重新定位所识别的次优定位单元引脚，从而识别次优定位单元引脚。

    Method for performing coupling analysis
    7.
    发明授权
    Method for performing coupling analysis 失效
    执行耦合分析的方法

    公开(公告)号：US06546529B1

    公开(公告)日：2003-04-08

    申请号：US09677362

    申请日：2000-10-02

    申请人： Allan H. Dansky ,  Michael A. Bowen ,  Peter J. Camporese ,  Alina Deutsch ,  Howard H. Smith

    发明人： Allan H. Dansky ,  Michael A. Bowen ,  Peter J. Camporese ,  Alina Deutsch ,  Howard H. Smith

    IPC分类号： G06F945

    CPC分类号： G06F17/5036

    摘要： Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.

    摘要翻译： 耦合噪声电压的确定性评估是许多物理和电气参数的函数，如布线级别，宽度，间距，网络拓扑，drv阻抗和转换速率。 该评估需要电气建模和后续电路仿真来评估这些参数的灵敏度。 这些敏感性可以归类为可以通过提取的物理设计数据直接相关联的耦合准则。 本发明公开了当耦合噪声电压计算通常需要的所有参数不可用时，在集成电路设计早期使用耦合指南表的技术的开发和实现。 步骤包括：创建集成电路的扁平布线图，识别集成电路上的耦合线段，跟踪集成电路上的导线互连图案，导出耦合的线段的电参数，以及生成具有 用于多个电参数的参数。 耦合准则表中的参数应用于导出的电气参数，并生成报告，列出导出的电气参数不符合耦合指南表中的参数。

    Routing program method for positioning unit pins in a hierarchically designed VLSI chip
    8.
    发明授权
    Routing program method for positioning unit pins in a hierarchically designed VLSI chip 失效

    公开(公告)号：US06460169B1

    公开(公告)日：2002-10-01

    申请号：US09422040

    申请日：1999-10-21

    申请人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    发明人： Peter J. Camporese ,  Allan H. Dansky ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5077

    摘要： A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.

    High speed low power current controlled gate circuit
    10.
    发明授权
    High speed low power current controlled gate circuit 失效
    高速低功耗电流控制门电路

    公开(公告)号：US4605870A

    公开(公告)日：1986-08-12

    申请号：US478613

    申请日：1983-03-25

    申请人： Allan H. Dansky ,  John P. Norsworthy

    发明人： Allan H. Dansky ,  John P. Norsworthy

    IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K3/33 ,  H03K17/04 ,  H03K19/088

    CPC分类号： H03K19/013 ,  H03K19/001

    摘要： The invention pertains to semiconductor circuitry, and more particularly to a class of circuitry known as current controlled gate circuits for driving very large scale integrated circuit gate arrays; the novel circuit can achieve much lower speed-power products than other circuitry, such as the well known T.sup.2 L circuitry; the circuit includes push-pull drive and it provides negligible DC current in both DC states, that is, On and Off.

    摘要翻译： 本发明涉及半导体电路，更具体地，涉及一类称为用于驱动非常大规模集成电路门阵列的电流控制门电路的电路; 新颖的电路可以实现比其他电路（例如众所周知的T2L电路）低得多的速度功率产品; 该电路包括推挽式驱动器，并且在两种DC状态下，即On和Off都提供可忽略的直流电流。