发明授权
- 专利标题: Timing margin alteration via the insulator of a SOI die
- 专利标题(中): 通过SOI芯片的绝缘体的时序边缘变化
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申请号: US09864665申请日: 2001-05-23
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公开(公告)号: US06621288B1公开(公告)日: 2003-09-16
- 发明人: Michael R. Bruce , Rama R. Goruganthu
- 申请人: Michael R. Bruce , Rama R. Goruganthu
- 主分类号: G01R3126
- IPC分类号: G01R3126
摘要:
Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by operating a die and detecting a response that is used to analyze selected characteristics of the die. According to an example embodiment of the present invention, a die having a thinned backside is provided for analysis. The die is operated so that one or more portions of circuitry in the die are near a state-changing transition between a failed mode and a recovered mode. An electron-beam probe is directed to the thinned backside, and the probe electrically couples a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry and, thereby, causes the circuitry to undergo a state-changing transition. A response from the circuitry related to the transition is detected and used to analyze the die. In this manner, portions of the die being affected by altered timing margins can be detected.
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