Invention Grant
- Patent Title: Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
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Application No.: US10264951Application Date: 2002-10-04
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Publication No.: US06624494B2Publication Date: 2003-09-23
- Inventor: Richard A. Blanchard , Jean-Michel Guillot
- Applicant: Richard A. Blanchard , Jean-Michel Guillot
- Main IPC: H01L2358
- IPC: H01L2358

Abstract:
A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
Public/Granted literature
- US20030068863A1 Method for fabricating a power semiconductor device having a floating island voltage sustaining layer Public/Granted day:2003-04-10
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