公开(公告)号：US06831296B1

公开(公告)日：2004-12-14

申请号：US10713110

申请日：2003-11-17

Applicant: Ki Hyun Lee ,  Seong Bong Kim

Inventor： Ki Hyun Lee ,  Seong Bong Kim

IPC: H01L2358

CPC classification number: G01R31/2886 ,  G01R31/2893

Abstract: A device for seating a semiconductor device in a semiconductor test handler is provided. The device includes a plate having a plurality of device seating members each for seating the semiconductor device. The device also includes a latch rotatably mounted to one side of the device seating member for pressing down or freeing the semiconductor device seated on the device seating member. A latch operating means for causing the latch to press down the semiconductor device when the semiconductor device is seated on the device seating member is also included. The provided device also releases the pressing down action when the semiconductor device is seated on the device seating member and when the semiconductor device is taken away from the device seating member, thereby seating the semiconductor device on the device seating device accurately and positively.

Abstract translation: 提供了一种用于将半导体器件置于半导体测试处理器中的装置。 该装置包括具有多个装置就座部件的板，每个装置就座部件用于安置半导体装置。 该装置还包括可旋转地安装到装置座构件的一侧的闩锁，用于压下或释放坐在装置座椅构件上的半导体装置。 还包括一个闩锁操作装置，用于当半导体装置就座在装置座椅部件上时使闩锁压下半导体装置。 当半导体器件位于器件座部件上时，当半导体器件被从器件座位部件上取走时，所提供的器件还释放按压动作，从而准确而准确地将半导体器件固定在器件座椅器件上。

公开(公告)号：US06828599B2

公开(公告)日：2004-12-07

申请号：US10381988

申请日：2003-06-12

Applicant: Chang Tae Kim

Inventor： Chang Tae Kim

IPC: H01L2358

CPC classification number: H01L33/08 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2924/00014

Abstract: The present invention relates to a semiconductor LED device comprising a pumping layer with high light emitting efficiency and an active layer with smaller bandgap converting the absorbed light into any kinds of light of wavelength as required, which generates light from the AlGaInN pumping layer containing less In, projects the rays of light on the active layer containing more In, lets the required light of wavelength emit and decreases the blue shift caused by electric current, thereby increasing the light emitting efficiency and emitting lights with more than two wavelengths from one Led device. This invention enables to obtain various light of wavelength from one device and form the element through only one epitaxy process, thereby increasing reproductivity, yield, and efficiency by not using the fluorescent materials lowering the efficiency when forming white light.

Abstract translation: 本发明涉及一种半导体LED器件，其包括具有高发光效率的泵浦层和具有较小带隙的有源层，其将吸收的光转换成所需的波长的任何种类的光，其从包含较少In的AlGaInN泵浦层产生光 在含有更多In的有源层上投射光线，使所需波长的光发射并减少由电流引起的蓝移，从而增加发光效率并从一个LED装置发射具有两个以上波长的光。 本发明能够从一个器件获得各种波长的光并通过仅一个外延工艺形成元件，从而通过不使用在形成白光时降低效率的荧光材料来提高再现性，产率和效率。

公开(公告)号：US06822259B1

公开(公告)日：2004-11-23

申请号：US10126193

申请日：2002-04-19

Applicant: Zhigang Wang ,  Nian Yang ,  Xin Guo

Inventor： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC: H01L2358

CPC classification number: H01L21/28273 ,  G11C16/04 ,  G11C29/006 ,  G11C2029/0403 ,  G11C2029/5002

Abstract: A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.

Abstract translation: 一种用于测试包括堆叠浮栅结构的半导体的方法和装置。 浮动门被编程（710）。 电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。 在应力之后，测量漏极电流与栅极电压的关系（730）。 编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。 更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。 通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。 以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

公开(公告)号：US06815805B2

公开(公告)日：2004-11-09

申请号：US10758518

申请日：2004-01-15

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L2358

CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/792 ,  Y10T29/41

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 在可擦除可编程只读存储器（EPROM）器件中的隧道电介质被含氢化合物，特别是氨氮化。 因此，氢与氮一起并入隧道电介质中。 蚀刻并完成了栅极堆叠，包括保护性侧壁间隔物和电介质盖，并且叠置有对羟基和氢物质的屏障。 尽管衬垫有利地将杂质扩散减少到隧道电介质和衬底界面，但是在任何随后的氢退火中也可以减少氢扩散。 然而，在先前暴露于氨中时，向隧道电介质提供氢。

公开(公告)号：US06812488B2

公开(公告)日：2004-11-02

申请号：US10615686

申请日：2003-07-08

Applicant: Guobiao Zhang

Inventor： Guobiao Zhang

IPC: H01L2358

CPC classification number: H01L29/76 ,  G11C7/18 ,  G11C17/06 ,  G11C17/14 ,  G11C29/822 ,  G11C29/846 ,  H01L23/58 ,  H01L27/0688

Abstract: The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

Abstract translation: 电可编程三维存储器（EP-3DM）可用于承载用于测试电路（CUT）的测试数据和/或测试数据种子。 当与CUT集成时，EP-3DM对CUT的布局影响最小。 显然，具有集成EP-3DM的CUT支持IC自检。 此外，利用CUT具有大的带宽，基于EP-3DM的IC自检能够进行高速测试。

公开(公告)号：US06798043B2

公开(公告)日：2004-09-28

申请号：US10038352

申请日：2002-01-02

Applicant: Kurt G. Steiner ,  Susan Vitkavage ,  Steve Lytle ,  Gerald Gibson ,  Scott Jessen

Inventor： Kurt G. Steiner ,  Susan Vitkavage ,  Steve Lytle ,  Gerald Gibson ,  Scott Jessen

IPC: H01L2358

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Abstract translation: 膜结构包括低k电介质膜和N-H基源膜，例如阻挡层膜，蚀刻停止膜和硬掩模膜。 在低k电介质膜和相邻的N-H基膜之间插入TEOS氧化物膜，其抑制胺或其它N-H碱从N-H基底膜向低k电介质膜的扩散。 可以使用DUV光刻和化学放大的光致抗蚀剂来对膜结构进行图案化，因为在低k电介质膜中不存在碱基以中和化学放大光致抗蚀剂中的酸催化剂。

公开(公告)号：US06794733B1

公开(公告)日：2004-09-21

申请号：US09590805

申请日：2000-06-09

Applicant: Frederick T. Brady ,  Murty S. Polavarapu

Inventor： Frederick T. Brady ,  Murty S. Polavarapu

IPC: H01L2358

CPC classification number: H01L21/823481 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0883 ,  H01L29/32 ,  H01L2924/0002 ,  Y10S257/921 ,  H01L2924/00

Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

Abstract translation: 在集成电路中，产生了当代加工技术的优点，但由电离辐射造成不可弥补的破坏。 集成电路采用众所周知的现代处理技术设计和制造，除了将某些称为“保护”器件的器件添加到集成电路中。 保护装置被制造成使得它们而不是集成电路上的其他装置对电离辐射敏感。 此外，保护装置以集成电路用电离辐射轰击的方式与集成电路上的超级设备耦合，保护装置短路并破坏了该设备的功能，因此，功能性 集成电路。

公开(公告)号：US06768133B2

公开(公告)日：2004-07-27

申请号：US10124453

申请日：2002-04-18

Applicant: Yasumasa Nishimura

Inventor： Yasumasa Nishimura

IPC: H01L2358

CPC classification number: G01R31/31937 ,  G01R31/319 ,  G01R31/31922

Abstract: The present invention comprises: a plurality of output terminals through which a signal from an internal circuit is output; buffer circuits, each provided between one of the plurality of output terminals and the internal circuit; and a delay circuit connected to the specific buffer, the delay circuit delaying the signal from the internal circuit. With this arrangement, it is possible to measure a delay time from an input test signal even when a super-high-speed device is tested.

Abstract translation: 本发明包括：输出来自内部电路的信号的多个输出端子; 缓冲电路，其分别设置在所述多个输出端子中的一个和所述内部电路之间; 以及连接到特定缓冲器的延迟电路，延迟电路延迟来自内部电路的信号。 通过这种布置，即使测试超高速装置，也可以从输入测试信号测量延迟时间。

公开(公告)号：US06765283B2

公开(公告)日：2004-07-20

申请号：US10201646

申请日：2002-07-24

Applicant: Takeshi Umemoto

Inventor： Takeshi Umemoto

IPC: H01L2358

CPC classification number: H01L21/76834 ,  H01L21/76808 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising: an underlayer interconnect layer; an interlayer dielectric film formed with a connection hole reaching the underlayer interconnect layer; and an upper interconnect layer buried in the connection hole, wherein the interlayer dielectric film includes an insulating film containing an impurity for detecting a first etching end point, a first insulating film, an insulating film containing an impurity for detecting a second etching end point and a second insulating film, these four films being laminated in this order.

Abstract translation: 一种半导体器件，包括：下层互连层; 形成有到达下层互连层的连接孔的层间绝缘膜; 以及埋入所述连接孔中的上互连层，其中所述层间电介质膜包括含有用于检测第一蚀刻终点的杂质的绝缘膜，第一绝缘膜，含有用于检测第二蚀刻终点的杂质的绝缘膜， 第二绝缘膜，这四个膜依次层压。

公开(公告)号：US06762432B2

公开(公告)日：2004-07-13

申请号：US10114707

申请日：2002-04-01

Applicant: Robert W. Rumsey

Inventor： Robert W. Rumsey

IPC: H01L2358

CPC classification number: G03F7/70633 ,  G03F7/70658

Abstract: A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test structure pattern is stepped between fields on a wafer, the first comb and the second comb at least partially overlap on photoresist over a scribe lane between the fields. When the photoresist is developed, the overlap of the first comb and the second comb generates a metal comb. Electrical continuity is checked for the metal tines of the metal comb to determine the misalignment of the fields.

Abstract translation: 测试结构图案包括具有第一组尖齿的第一梳和具有与第一组尖相同的宽度和间隔的第二组尖齿的第二梳。 当测试结构图案在晶片上的场之间步进时，第一梳和第二梳至少部分地在场之间的划线上的光致抗蚀剂上重叠。 当光致抗蚀剂显影时，第一梳和第二梳的重叠产生金属梳。 检查金属梳子的金属齿的电连续性以确定场的不对准。