发明授权
- 专利标题: Circuit for capturing frame sync signal in receiver
- 专利标题(中): 用于在接收机中捕获帧同步信号的电路
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申请号: US09581259申请日: 2000-06-27
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公开(公告)号: US06625239B1公开(公告)日: 2003-09-23
- 发明人: Kenichi Shiraishi , Akihiro Horii
- 申请人: Kenichi Shiraishi , Akihiro Horii
- 优先权: JP9-368190 19971229
- 主分类号: H04L700
- IPC分类号: H04L700
摘要:
I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by &pgr;/4, 2&pgr;/4, and 3&pgr;/4 counterclockwise. When a pattern having is a difference of several bits at most from a frame-synchronizing signal is captured from B0 to B3 by first comparing circuits 60 to 63 and thereafter, a pattern having a difference of several bits at most from a superframe-identifying signal is captured by second comparing circuits 64 to 67 after a predetermined certain time, a frame-synchronizing-signal-capturing-signal generating circuit (90) outputs a frame-synchronizing-signal capturing signal (SYN).