发明授权
US06625802B2 Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
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用于修改芯片布局以最小化由EUV光刻中的光斑变化引起的管芯内CD变化的方法
- 专利标题： Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
- 专利标题（中）： 用于修改芯片布局以最小化由EUV光刻中的光斑变化引起的管芯内CD变化的方法
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申请号： US10061615申请日： 2002-02-01
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公开(公告)号： US06625802B2公开(公告)日： 2003-09-23
- 发明人: Vivek K. Singh , John Ernst Bjorkholm , Francisco A. Leon
- 申请人： Vivek K. Singh , John Ernst Bjorkholm , Francisco A. Leon
- 主分类号： G06F1750
- IPC分类号： G06F1750
摘要：
A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
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