发明授权
US06630377B1 Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process 有权
制造与CMOS工艺兼容的高增益垂直双极结晶体管结构的方法

  • 专利标题: Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
  • 专利标题(中): 制造与CMOS工艺兼容的高增益垂直双极结晶体管结构的方法
  • 申请号: US10246228
    申请日: 2002-09-18
  • 公开(公告)号: US06630377B1
    公开(公告)日: 2003-10-07
  • 发明人: Shesh Mani PandayAlan ShafiYong Ju
  • 申请人: Shesh Mani PandayAlan ShafiYong Ju
  • 主分类号: H01L218238
  • IPC分类号: H01L218238
Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
摘要:
An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.
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