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    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
    3.
    发明授权
    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures 有权
    肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法

    公开(公告)号：US08207559B2

    公开(公告)日：2012-06-26

    申请号：US12498141

    申请日：2009-07-06

    申请人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    发明人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    IPC分类号： H01L29/66

    CPC分类号： H01L27/095 ,  H01L27/0207 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/808 ,  H01L29/812

    摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.

    摘要翻译： 根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。 结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。 此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。 根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接 场效应晶体管（JFET）。 在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。 根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。 该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。 掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。 此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。 这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

    Method of manufacturing self-aligned n and p type stripes for a superjunction device
    4.
    发明授权
    Method of manufacturing self-aligned n and p type stripes for a superjunction device 有权
    制造用于超结装置的自对准n和p型条纹的方法

    公开(公告)号：US07238577B1

    公开(公告)日：2007-07-03

    申请号：US11132032

    申请日：2005-05-18

    申请人： Zia Alan Shafi

    发明人： Zia Alan Shafi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0634 ,  H01L21/266 ,  H01L29/66681 ,  H01L29/7824

    摘要： A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alternating stripes enables improvements in on-state resistance, while ensuring that the superjunction device is fully manufacturable. Only one masking step is required to fabricate the alternating N-type and P-type stripes.

    摘要翻译： 提供了一种用于获得形成超结功率器件的电压阻挡区域的极细间距N型和P型条纹的方法。 条纹是自对准的，不会有对准公差。 交替条纹的自对准精细间距使得能够改善导通状态电阻，同时确保超级结装置是完全可制造的。 只需要一个屏蔽步骤来制造交替的N型和P型条纹。

    Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
    5.
    发明授权
    Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process 有权
    制造与CMOS工艺兼容的高增益垂直双极结晶体管结构的方法

    公开(公告)号：US06828635B2

    公开(公告)日：2004-12-07

    申请号：US10655475

    申请日：2003-09-04

    申请人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

    发明人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

    IPC分类号： H01L2976

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

    摘要： An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

    摘要翻译： 实现了可与CMOS FET处理集成的改进的NPN双极晶体管。 晶体管使用CMOS工艺和一个额外的掩模和注入步骤在衬底上形成。 使用CMOS N阱形成集电极触点（达到），P阱用于形成基极。 在N个阱，P个阱和浅沟槽隔离区之下形成N个掺杂的第三阱，以提供子集电极。 由于P阱不通过STI注入，所以基极宽度减小，电流增益增加。 在基极上形成的栅电极掩模元件分离发射极和基极接触区域，改善发射极对基极击穿电压。 然后，CMOS源极/漏极N型注入器在发射极区域中形成发射极，并在集电极触点中形成欧姆接触。 源极/漏极P型注入器形成欧姆基极触点以完成双极晶体管。

    Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
    8.
    发明授权
    Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process 有权
    制造与CMOS工艺兼容的高增益垂直双极结晶体管结构的方法

    公开(公告)号：US06630377B1

    公开(公告)日：2003-10-07

    申请号：US10246228

    申请日：2002-09-18

    申请人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

    发明人： Shesh Mani Panday ,  Alan Shafi ,  Yong Ju

    IPC分类号： H01L218238

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

    摘要： An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

    摘要翻译： 实现了可与CMOS FET处理集成的改进的NPN双极晶体管。 晶体管使用CMOS工艺和一个额外的掩模和注入步骤在衬底上形成。 使用CMOS N阱形成集电极触点（达到），P阱用于形成基极。 在N个阱，P个阱和浅沟槽隔离区之下形成N个掺杂的第三阱，以提供子集电极。 由于P阱不通过STI注入，所以基极宽度减小，电流增益增加。 在基极上形成的栅电极掩模元件分离发射极和基极接触区域，改善发射极对基极击穿电压。 然后，CMOS源极/漏极N型注入器在发射极区域中形成发射极，并在集电极触点中形成欧姆接触。 源极/漏极P型注入器形成欧姆基极触点以完成双极晶体管。