Invention Grant
- Patent Title: Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor
-
Application No.: US10160630Application Date: 2002-06-03
-
Publication No.: US06635545B2Publication Date: 2003-10-21
- Inventor: Josef Böck , Wolfgang Klein , Herbert Schäfer , Martin Franosch , Thomas Meister , Reinhard Stengl
- Applicant: Josef Böck , Wolfgang Klein , Herbert Schäfer , Martin Franosch , Thomas Meister , Reinhard Stengl
- Priority: DE19958062 19991202
- Main IPC: H01L21331
- IPC: H01L21331

Abstract:
The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.
Public/Granted literature
Information query