公开(公告)号：US06835628B2

公开(公告)日：2004-12-28

申请号：US09992880

申请日：2001-11-05

申请人： James D. Beasom

发明人： James D. Beasom

IPC分类号： H01L21331

CPC分类号： H01L27/0658 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/067 ,  H01L27/0811

摘要： The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

摘要翻译： 本发明涉及具有MOS电容器的集成电路。 在一个实施例中，形成集成电路的方法包括在衬底的表面上形成氧化物层，所述衬底具有多个隔离岛。 每个隔离岛用于形成半导体器件。 对氧化物层进行构图以暴露衬底表面的预定区域。 沉积覆盖氧化物层的氮化物层和衬底的暴露的表面区域。 将离子注入氮化物层，其中氮化物层是用于注入离子的注入屏。 在形成电容器时使用氮化物层作为电容器电介质。 此外，进行干蚀刻以形成延伸穿过氮化物层并通过氧化物层的接触开口，以接触形成在衬底中的选定器件区域。

公开(公告)号：US06830982B1

公开(公告)日：2004-12-14

申请号：US10290976

申请日：2002-11-07

申请人： David Howard ,  Marco Racanelli ,  Greg D. U'Ren

发明人： David Howard ,  Marco Racanelli ,  Greg D. U'Ren

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/66272

摘要： According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.

摘要翻译： 根据一个示例性实施例，NPN双极晶体管包括位于集电极上方的基极层，其中基极层包含本征基极区域和外部基极区域。 NPN双极晶体管可以是例如NPN硅 - 锗异质结双极晶体管。 基层可以是例如硅 - 锗。 根据该示例性实施例，NPN双极晶体管还包括位于基极层之上的覆盖层，其中覆盖层的一部分位于外部本体区域之上，并且其中覆盖层的位于外部基极区域之上的部分 包括铟掺杂剂。 盖层可以是例如多晶硅。 根据该示例性实施例，NPN双极晶体管还可以包括位于本征基极区域上方的发射极。 发射极可以是例如多晶硅。

公开(公告)号：US06787427B2

公开(公告)日：2004-09-07

申请号：US10676171

申请日：2003-10-01

申请人： David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

发明人： David R. Greenberg ,  Basanth Jagannathan ,  Shwu-Jen Jeng ,  Joseph T. Kocis ,  Samuel C. Ramac ,  David M. Rockwell

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.

摘要翻译： 提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。 具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。 原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。 包括上述双层发射体的SiGe HBT结构也在此描述。

公开(公告)号：US06774002B2

公开(公告)日：2004-08-10

申请号：US10279549

申请日：2002-10-23

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21331

CPC分类号： H01L29/66287

摘要： The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window. A second polysilicon layer is formed over the expitaxy base and the emitter window, wherein the second polysilicon layer has the second type ion. Finally, an etching process is introduced to etch the second polysilicon layer to form emitter plug. That is self-aligned to the emitter window.

公开(公告)号：US06762106B2

公开(公告)日：2004-07-13

申请号：US10326059

申请日：2002-12-23

申请人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

发明人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

IPC分类号： H01L21331

CPC分类号： H01L29/7378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

摘要翻译： 包含Si缓冲层，SiGe间隔层，渐变SiGe层和Si覆盖层的Si / SiGe层在对应于集电极开口的区域中外延生长，而多晶层沉积在氮化物膜的上表面上 ，以及氧化膜和氮化物膜的侧表面。 在这种情况下，首先形成Si缓冲层，然后形成诸如SiGe间隔层的其它层，从而确保非选择性外延生长。 然后，在氮化物膜上沉积多晶层。

公开(公告)号：US06756281B2

公开(公告)日：2004-06-29

申请号：US10096742

申请日：2002-03-14

申请人： Paul Enquist

发明人： Paul Enquist

IPC分类号： H01L21331

CPC分类号： H01L29/7722 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

摘要： A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

摘要翻译： 一种半导体器件及其制造方法。 发射极区域与基极区域对称地形成为自对中和自对准。 使用前端处理技术，集电极形成为与基极区域和发射极区域对称自对准。 可以使用背面处理技术使收集器区域进一步与基部区域自身居中。 自对准和自对中结构的对称结构实际上消除了器件中的寄生元件，显着提高器件性能。 该器件的可扩展性约为0.1微米。 该方法还提供对称设备的商业制造所需的设备特性的可再现性和可重复性。

公开(公告)号：US06750109B2

公开(公告)日：2004-06-15

申请号：US10064305

申请日：2002-07-01

申请人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

发明人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

IPC分类号： H01L21331

CPC分类号： H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

摘要翻译： 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。 整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

公开(公告)号：US06740561B2

公开(公告)日：2004-05-25

申请号：US10093791

申请日：2002-03-07

申请人： Yoshifumi Yoshida ,  Jun Osanai

发明人： Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21331

CPC分类号： H01L21/8236 ,  H01L21/823857

摘要： There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.

摘要翻译： 提供了一种提高驱动能力和小型化的半导体器件。 P型晶体管由表面沟道型晶体管组成，使得沟道长度容易降低。 因此，促进了驱动能力的提高和小型化。 此外，由于栅极绝缘膜被氮化，栅极绝缘膜的可靠性得到改善，并且可以防止包含在p型多晶硅栅电极中的硼朝向沟道区域的通过。 形成栅极绝缘膜的步骤，对栅极绝缘膜进行氮化的步骤，使用惰性气体进行热处理的步骤，在栅极绝缘膜上形成栅电极的步骤，以及引入p型绝缘膜的步骤， 进行栅极电极的杂质化。 因此，构成表面沟道P型晶体管和埋入沟道N型晶体管。

公开(公告)号：US06730572B2

公开(公告)日：2004-05-04

申请号：US10347230

申请日：2003-01-21

申请人： Key-Min Lee ,  Jae-Gyung Ahn

发明人： Key-Min Lee ,  Jae-Gyung Ahn

IPC分类号： H01L21331

CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L21/823835

摘要： A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

摘要翻译： 一种形成硅化物的方法，特别是在其中p型栅极中的多晶硅晶粒以临界注入剂量重新掺杂诸如As等的n型杂质的CMOS器件中。 这增加了多晶硅的晶粒尺寸，这也通过在其随后的工艺步骤中确保热稳定性而降低了薄层电阻。 本发明通常包括形成未掺杂的多晶硅层，用p型杂质离子掺杂多晶硅层，用掺杂p掺杂多晶硅层的离子掺杂，所述离子通过加热而增加多晶硅层的晶粒尺寸，在 双掺杂多晶硅层，并且通过使二掺杂多晶硅层的一部分与金属层反应而形成硅化物层。

公开(公告)号：US06713360B2

公开(公告)日：2004-03-30

申请号：US10218027

申请日：2002-08-12

申请人： Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

发明人： Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

IPC分类号： H01L21331

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/1083

摘要： The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.

摘要翻译： 本发明提供了一种通过将掺杂剂材料（116）注入到半导体晶片中而在半导体晶片中形成晶体管结的方法，将卤素材料（110）注入到半导体晶片（102）中，选择氟剂量和能量 定制晶体管的一个或多个特性，以选择的剂量和能量将氟注入到半导体晶片中，使用热处理激活掺杂剂材料并退火半导体晶片以除去残留的氟。 晶体管的一个或多个特性可以包括卤素偏析，卤素扩散，晕轮廓的锐度，掺杂剂激活，掺杂剂分布锐度，驱动电流，底壁电容或近边缘电容。