Invention Grant
- Patent Title: Power distribution design method for stacked flip-chip packages
- Patent Title (中): 堆叠倒装芯片封装的配电设计方法
-
Application No.: US10068537Application Date: 2002-02-06
-
Publication No.: US06635970B2Publication Date: 2003-10-21
- Inventor: Jerome B. Lasky , Edward J. Nowak , Edmund J. Sprogis
- Applicant: Jerome B. Lasky , Edward J. Nowak , Edmund J. Sprogis
- Main IPC: H01L2348
- IPC: H01L2348

Abstract:
A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.
Public/Granted literature
- US20030146517A1 POWER DISTRIBUTION DESIGN METHOD FOR STACKED FLIP-CHIP PACKAGES Public/Granted day:2003-08-07
Information query