公开(公告)号：US06635970B2

公开(公告)日：2003-10-21

申请号：US10068537

申请日：2002-02-06

申请人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

发明人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

摘要翻译： 片上芯片模块及相关的形成方法。 第一和第二半导体芯片被耦合在一起。 第一芯片包括分别在第一芯片的第一和第二侧上的第一布线层和第一导电基板。 电源电压VDD适于电耦合到第一芯片的第二侧。 第二芯片包括分别在第二芯片的第一和第二侧上的第二布线层和第二导电基板。 接地电压GND适于电耦合到第二芯片的第二侧。 第一芯片的第一侧电耦合到第二芯片的第一侧。 电源电压VDD和接地电压GND适于为第一和第二芯片提供电力。

公开(公告)号：US06727118B2

公开(公告)日：2004-04-27

申请号：US10462273

申请日：2003-06-16

申请人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

发明人： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC分类号： H01L2144

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

摘要翻译： 片上芯片模块及相关的形成方法。 第一和第二半导体芯片被耦合在一起。 第一芯片包括分别在第一芯片的第一和第二侧上的第一布线层和第一导电基板。 电源电压VDD适于电耦合到第一芯片的第二侧。 第二芯片包括分别在第二芯片的第一和第二侧上的第二布线层和第二导电基板。 接地电压GND适于电耦合到第二芯片的第二侧。 第一芯片的第一侧电耦合到第二芯片的第一侧。 电源电压VDD和接地电压GND适于为第一和第二芯片提供电力。

公开(公告)号：US06436744B1

公开(公告)日：2002-08-20

申请号：US09809888

申请日：2001-03-16

申请人： Andres Bryant ,  Jerome B. Lasky ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

发明人： Andres Bryant ,  Jerome B. Lasky ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78645

摘要： A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the substrate conductor is provided below a third side of the gate. The buried body contact does not extend to the top surface of the silicon body. The body contact is separated from the gate by a second dielectric having a thickness typically greater than that of the gate dielectric. The body contact is a plug of conductive material, and the second dielectric coats the body contact under the gate. The FET can be used in an SRAM circuit or other type of circuit having a silicon-on-insulator (SOI) construction.

摘要翻译： 一种具有SOI FET的半导体器件，其在导电基板上的绝缘层上包括硅体。 栅极电介质和栅极设置在硅体的表面上，源极和漏极设置在栅极的两侧。 在栅极的第三侧的下方设置与基板导体的埋入体接触。 埋体体接触不延伸到硅体的顶表面。 通过具有通常大于栅极电介质的厚度的厚度的第二电介质将体接触件与栅极分离。 身体接触是导电材料的塞子，第二电介质在门下方涂覆身体接触。 该FET可用于具有绝缘体上硅（SOI）结构的SRAM电路或其他类型的电路中。

公开(公告)号：US07183573B2

公开(公告)日：2007-02-27

申请号：US09978528

申请日：2001-10-17

申请人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

发明人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

IPC分类号： H01L21/00 ,  H01L21/238

CPC分类号： H01L29/66643 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/812

摘要： A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

摘要翻译： 公开了一种绝缘体上硅晶体管，其具有与身体的肖特基接触。 肖特基接触可以形成在栅极导体的源极和/或漏极侧。 在栅极导体的侧壁上形成有至少一部分是一次性的间隔物。 延伸区域设置在衬底下延伸在间隔物和栅极导体之下。 源极和漏极扩散区域被注入邻近延伸区域的衬底中。 然后移除间隔件的一次性部分以暴露延伸区域的一部分。 至少在延伸区域中形成金属层，导致肖特基接触。

公开(公告)号：US6153934A

公开(公告)日：2000-11-28

申请号：US126577

申请日：1998-07-30

申请人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

发明人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L23/48

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L21/28568

摘要： A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

公开(公告)号：US5185294A

公开(公告)日：1993-02-09

申请号：US797506

申请日：1991-11-22

申请人： Chung H. Lam ,  Jerome B. Lasky ,  Craig M. Hill ,  James S. Nakos ,  Steven J. Holmes ,  Stephen F. Geissler ,  David K. Lord

发明人： Chung H. Lam ,  Jerome B. Lasky ,  Craig M. Hill ,  James S. Nakos ,  Steven J. Holmes ,  Stephen F. Geissler ,  David K. Lord

IPC分类号： H01L21/28 ,  H01L21/223 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H01L29/43

CPC分类号： H01L21/32134 ,  H01L21/768

摘要： The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent boron out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

公开(公告)号：US4799990A

公开(公告)日：1989-01-24

申请号：US44374

申请日：1987-04-30

申请人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

发明人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Paul C. Parries ,  Francis R. White

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/76224

摘要： A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

公开(公告)号：US07173303B2

公开(公告)日：2007-02-06

申请号：US10695335

申请日：2003-10-28

申请人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

发明人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L29/10 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78636

摘要： The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

摘要翻译： 本发明提供一种用于制造具有双栅极和双通道的金属氧化物半导体场效应晶体管（MOSFET）的方法，其中栅极区域与沟道区域和源极/漏极扩散接合点自对准。 本发明还涉及使用本发明的方法形成的FIN MOSFFET结构。

公开(公告)号：US06793735B2

公开(公告)日：2004-09-21

申请号：US09748965

申请日：2000-12-27

申请人： Marc W. Cantell ,  Jerome B. Lasky ,  Ronald J. Line ,  William J. Murphy ,  Kirk D. Peterson ,  Prabhat Tiwari

发明人： Marc W. Cantell ,  Jerome B. Lasky ,  Ronald J. Line ,  William J. Murphy ,  Kirk D. Peterson ,  Prabhat Tiwari

IPC分类号： C23C1600

CPC分类号： H01L21/28518 ,  Y10S414/139 ,  Y10S438/906 ,  Y10S438/908

摘要： A method and apparatus are provided for forming a silicide on a semiconductor substrate by integrating under a constant vacuum the processes of removing an oxide from a surface of a semiconductor substrate and depositing a metal on the cleaned surface without exposing the cleaned surface to air. The method and apparatus of the present invention eliminates the exposure of the cleaned substrate to air between the oxide removal and metal deposition steps. This in-situ cleaning of the silicon substrate prior to cobalt deposition provides a cleaner silicon substrate surface, resulting in enhanced formation of cobalt silicide when the cobalt layer is annealed.

摘要翻译： 提供一种方法和装置，用于通过在恒定真空下整合从半导体衬底的表面去除氧化物并在清洁的表面上沉积金属而不将清洁的表面暴露于空气的过程来在半导体衬底上形成硅化物。 本发明的方法和装置消除了在氧化物去除和金属沉积步骤之间清洁的衬底对空气的暴露。 在钴沉积之前对硅衬底的原位清洁提供了更清洁的硅衬底表面，当钴层退火时，导致硅化钴的形成增强。

公开(公告)号：US06689650B2

公开(公告)日：2004-02-10

申请号：US09965288

申请日：2001-09-27

申请人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

发明人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

IPC分类号： H01L2100

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78636

摘要： The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

摘要翻译： 本发明提供一种用于制造具有双栅极和双通道的金属氧化物半导体场效应晶体管（MOSFET）的方法，其中栅极区域与沟道区域和源极/漏极扩散接合点自对准。 本发明还涉及使用本发明的方法形成的FIN MOSFFET结构。