发明授权
- 专利标题： Semiconductor memory device that operates in synchronization with a clock signal
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申请号： US10135507申请日： 2002-05-01
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公开(公告)号： US06636455B2公开(公告)日： 2003-10-21
- 发明人: Yukiko Maruyama , Seiji Sawada
- 申请人： Yukiko Maruyama , Seiji Sawada
- 优先权： JP2001-271600 20010907
- 主分类号： G11C800
- IPC分类号： G11C800
摘要：
This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.
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