发明授权
US06636825B1 Component level, CPU-testable, multi-chip package using grid arrays
有权
组件级，CPU可测试，使用网格阵列的多芯片封装
- 专利标题： Component level, CPU-testable, multi-chip package using grid arrays
- 专利标题（中）： 组件级，CPU可测试，使用网格阵列的多芯片封装
-
申请号： US09364832申请日： 1999-07-30
-
公开(公告)号： US06636825B1公开(公告)日： 2003-10-21
- 发明人: Deviprasad Malladi , Renukanthan Raman , Christopher D. Furman
- 申请人： Deviprasad Malladi , Renukanthan Raman , Christopher D. Furman
- 主分类号： G01R3100
- IPC分类号： G01R3100
摘要：
A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.