公开(公告)号：US06636825B1

公开(公告)日：2003-10-21

申请号：US09364832

申请日：1999-07-30

申请人： Deviprasad Malladi ,  Renukanthan Raman ,  Christopher D. Furman

发明人： Deviprasad Malladi ,  Renukanthan Raman ,  Christopher D. Furman

IPC分类号： G01R3100

CPC分类号： G11C29/56016 ,  G01R31/2891 ,  G11C29/48

摘要： A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.

摘要翻译： 一种用于在包括测试基板，微处理器和一个或多个相关联的计算机组件（例如SRAM，DRAM和ROM）的子系统上进行电接受测试的方法。 提供了一种引脚网格阵列，球栅阵列，线阵列或等效测试连接器系统，其允许直接寻址微处理器和每个相关组件的选定电路。 首先在一起测试微处理器加衬底。 如果该测试成功，则相关组件然后被添加，最好一次添加，并且新的子系统被测试。 如果特定的子系统测试失败，则可能会将故障原因隔离并删除，并且可以重新测试修改后的子系统。

公开(公告)号：US5386526A

公开(公告)日：1995-01-31

申请号：US779388

申请日：1991-10-18

申请人： Samir Mitra ,  Renukanthan Raman ,  Joseph Petollno

发明人： Samir Mitra ,  Renukanthan Raman ,  Joseph Petollno

IPC分类号： G06F12/08 ,  G06F12/06 ,  G06F13/00

CPC分类号： G06F12/0859

摘要： A cache memory controller and an associated method for fetching data are utilized to reduce the idle time of a central processing unit (CPU) of a computer system. Control circuitry and a plurality of cache fill status registers are provided to a cache controller to enable a data word to be fetched and returned to the CPU while a cache memory fill initiated due to a prior cache miss is still in progress. The data word is returned if the data word is stored in a main memory location which corresponds to a memory block offset of a main memory block frame currently being mapped into the cache memory. The data word is retrieved and returned to the CPU simultaneous with its writing into the cache memory, if the data word has not been written into the cache memory; otherwise, the data word is retrieved and returned to the CPU at the next dead cycle. As a result, CPU idle time due to cache read misses is reduced.

摘要翻译： 利用高速缓冲存储器控制器和用于取出数据的关联方法来减少计算机系统的中央处理单元（CPU）的空闲时间。 控制电路和多个高速缓存填充状态寄存器被提供给高速缓存控制器，以使数据字被取出并返回到CPU，同时由于先前的高速缓存未命中而启动的高速缓存存储器填充仍在进行中。 如果数据字被存储在与当前被映射到高速缓冲存储器中的主存储器块帧的存储器块偏移相对应的主存储器位置中，则返回数据字。 如果数据字未写入高速缓冲存储器，数据字被读取并返回到CPU同时写入高速缓冲存储器; 否则，数据字被检索并在下一个死循环返回给CPU。 结果，由于缓存读取未命中而导致的CPU空闲时间减少。