RAM circuit with redundant word lines
Abstract:
A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p−k locations of the pattern are unoccupied.
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