- 专利标题: Semiconductor integrated circuit device and manufacturing method thereof
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申请号: US10227799申请日: 2002-08-27
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公开(公告)号: US06649956B2公开(公告)日: 2003-11-18
- 发明人: Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
- 申请人: Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
- 优先权: JP9-164766 19970620
- 主分类号: H01L2972
- IPC分类号: H01L2972
摘要:
An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.