公开(公告)号：US06831337B2

公开(公告)日：2004-12-14

申请号：US10622052

申请日：2003-07-17

Applicant: Zhiqiang Wu ,  David B. Scott

Inventor： Zhiqiang Wu ,  David B. Scott

IPC: H01L2972

CPC classification number: H01L29/66659 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/7835

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract translation: 一种在半导体有源区（78）中形成晶体管（70）的方法。 该方法形成与半导体有源区域固定关系的栅极结构（G2），从而限定与第一栅极结构侧壁相邻的第一源极/漏极区域（R1）和邻近第二侧壁栅极的第二源极/漏极区域（R2） 结构体。 该方法还形成在第一源极/漏极区域中形成并在栅极结构下方延伸的轻掺杂扩散区域（801），其中轻掺杂扩散区域包括与栅极结构平行的方向上的变化的电阻。

公开(公告)号：US06818945B2

公开(公告)日：2004-11-16

申请号：US10404141

申请日：2003-04-02

Applicant: Yusuke Kawaguchi ,  Syotaro Ono ,  Akio Nakagawa

Inventor： Yusuke Kawaguchi ,  Syotaro Ono ,  Akio Nakagawa

IPC: H01L2972

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate of a first conductive type; a semiconductor layer of the first conductive type formed on the semiconductor substrate; a base layer of a second conductive type formed on the semiconductor layer; a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth; insulating films formed on side surfaces and bottoms of the trenches, respectively; source layers of the first conductive type formed on surface layer portions of the base layer between the trenches, respectively; stripe contact layers of the second conductive type formed each at centers of the surface layer portions of the base layer between the trenches, respectively; a gate electrode formed in every other trench among the plurality of columns of trenches; source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and the contact layers, respectively; and a drain electrode formed on a rear surface of the semiconductor substrate.

Abstract translation: 根据本发明的一个实施例的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底上的所述第一导电类型的半导体层; 形成在所述半导体层上的第二导电类型的基底层; 多个柱状的条形槽，以预定的距离从基底层的表面形成预定的深度; 分别形成在沟槽的侧表面和底部的绝缘膜; 分别形成在沟槽之间的基底层的表层部分上的第一导电类型的源极层; 分别在沟槽之间的基底层的表层部分的中心分别形成第二导电类型的条状接触层; 形成在所述多个沟槽列之间的每隔一个沟槽中的栅电极; 源极电极分别形成在不同于其中形成栅电极的沟槽之外的沟槽中，并分别在源极层和接触层上形成; 以及形成在所述半导体衬底的后表面上的漏电极。

公开(公告)号：US06815768B1

公开(公告)日：2004-11-09

申请号：US10699202

申请日：2003-10-31

Applicant: Hideaki Aochi

Inventor： Hideaki Aochi

IPC: H01L2972

CPC classification number: H01L29/66545 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

Abstract: A conductor film and a cap insulating film are sequentially formed, and a laminated film constituted of the cap insulating film and the conductor film is patterned, and then a gate electrode is formed. Next, source and drain diffusion regions are formed, and a first silicon nitride film is formed on a sidewall of the laminated film, and then a second silicon nitride film is formed on an entire surface, and further a silicon oxide film is deposited. Next, the silicon oxide film is left between the gate electrodes, and the second silicon nitride film on the laminated film is removed, and the cap insulating film left above the gate electrode is removed, and a metal silicide film is formed on a surface of the gate electrode, and then a third silicon nitride film is left on the gate electrode.

Abstract translation: 依次形成导体膜和帽绝缘膜，对盖绝缘膜和导体膜构成的层叠膜进行图案化，形成栅电极。 接下来，形成源极和漏极扩散区，并且在层压膜的侧壁上形成第一氮化硅膜，然后在整个表面上形成第二氮化硅膜，并且还沉积氧化硅膜。 接下来，将氧化硅膜留在栅电极之间，去除叠层膜上的第二氮化硅膜，去除留在栅电极上的帽绝缘膜，并在金属硅化物膜的表面上形成金属硅化物膜 栅电极，然后第三氮化硅膜留在栅电极上。

公开(公告)号：US06803652B2

公开(公告)日：2004-10-12

申请号：US09870952

申请日：2001-05-30

Applicant: Casey R. Winkel ,  Michael Z. Eckblad ,  Jeffrey J. Sopko

Inventor： Casey R. Winkel ,  Michael Z. Eckblad ,  Jeffrey J. Sopko

IPC: H01L2972

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat dissipation device having an integral load centering mechanism adapted to provide a location for contact between a spring clip and the heat dissipation device. The load centering mechanism is located in an area on the heat dissipation device which will provide a centered loading to a microelectronic die and constitutes substantially the only place where the spring clip contacts the heat dissipation device when the spring clip is providing a force against the heat dissipation device.

Abstract translation: 一种散热装置，其具有适于提供弹簧夹和散热装置之间的接触位置的整体式负载定心机构。 负载定心机构位于散热装置上的区域中，该区域将向微电子管芯提供中心负载，并且构成弹簧夹接触散热装置的唯一位置，当弹簧夹提供抵抗热量的力 消散装置

公开(公告)号：US06787875B2

公开(公告)日：2004-09-07

申请号：US10212419

申请日：2002-08-05

Applicant: Kenneth D. Brennan ,  Paul M. Gillespie

Inventor： Kenneth D. Brennan ,  Paul M. Gillespie

IPC: H01L2972

CPC classification number: H01L21/76897 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

公开(公告)号：US06787849B2

公开(公告)日：2004-09-07

申请号：US10357051

申请日：2003-02-03

Applicant: Masahiro Hayashi

Inventor： Masahiro Hayashi

IPC: H01L2972

CPC classification number: H01L21/823892 ,  H01L21/76202 ,  H01L21/823814 ,  H01L21/823878

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract translation: 实施例包括一种包括阱结构的半导体器件，使得能够以更高的集成密度形成阱区，并且可以以不同的电压彼此独立地驱动多个高压耐久晶体管，以及制造半导体器件的方法 。 半导体器件可以包括三阱，其包括形成在硅衬底中并且具有第一导电类型（P型）的第一阱，与第一阱相邻的第二阱，并且具有第二导电类型（N型） ）和形成在第二阱中并具有第一导电类型（P型）的第三阱。 在每个井中提供高压耐久MOSFET。 每个MOSFET在栅极绝缘层周围的相应阱中具有偏移区域。 偏移区域由设置在硅衬底上的偏移LOCOS层下方的低密度杂质层形成。

公开(公告)号：US06787451B2

公开(公告)日：2004-09-07

申请号：US10216792

申请日：2002-08-13

Applicant: Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

Inventor： Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

IPC: H01L2972

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02323 ,  H01L21/02329 ,  H01L21/02337 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract translation: 在具有SiO 2当量厚度为2nm以上的栅极绝缘膜的FET的制造方法中，能够将漏电流抑制到{部分（与现有的SiO 2膜相比为1/100以下）的SiO 2膜为0.5nm 以上的Si基板（多晶硅栅极）和高介电绝缘膜之间的边界处形成，并且使SiO 2膜的形成温度高于后续工序中的源极 - 漏极活​​化热处理温度，因此 可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低引起的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

公开(公告)号：US06784482B2

公开(公告)日：2004-08-31

申请号：US10361601

申请日：2003-02-11

Applicant: Katsutoshi Saeki

Inventor： Katsutoshi Saeki

IPC: H01L2972

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L29/7885

Abstract: The nonvolatile semiconductor memory device includes a first conductivity-type semiconductor substrate where an active region is created, a floating gate which is formed on the first conductivity-type semiconductor substrate, and a control gate which is formed on the floating gate. A first conductivity-type high concentration diffused region is formed in the non-overlapping region of the floating gate in the active region.

Abstract translation: 非易失性半导体存储器件包括形成有源区的第一导电型半导体衬底，形成在第一导电型半导体衬底上的浮置栅极和形成在浮置栅极上的控制栅极。 第一导电型高浓度扩散区域形成在有源区域中的浮置栅极的非重叠区域中。

公开(公告)号：US06764910B2

公开(公告)日：2004-07-20

申请号：US10371093

申请日：2003-02-21

Applicant: Hyuk-Ju Ryu ,  Jong-hyon Ahn

Inventor： Hyuk-Ju Ryu ,  Jong-hyon Ahn

IPC: H01L2972

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L29/6656

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件的结构包括具有由具有低栅极电阻和低寄生电容的第一和第二栅电极组成的T形结构的栅极电极和可有效抑制短沟道效应的晕圈离子注入区域。 该器件的制造方法能够进行高角度离子注入而不延长栅极到栅极空间。

公开(公告)号：US06744107B1

公开(公告)日：2004-06-01

申请号：US10325892

申请日：2002-12-23

Applicant: Ming-Dou Ker ,  Kuo-Chun Hsu ,  Wen-Yu Lo

Inventor： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Wen-Yu Lo

IPC: H01L2972

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge protection circuit. The electrostatic discharge protection circuit utilizes the non-uniform triggering of multi-finger gate-grounded NMOS. The source of the finger which has the potential to trigger on is coupled to the base terminal of all the parasitic bipolar transistor of all the other multi-finger gate-ground NMOS structures. Thus, the finger which has the potential to be triggered can be used as a triggering device to trigger the other finger devices during an ESD event. By using this method, the ESD protection NMOS or PMOS, realized with multi-finger layout structure, can be uniformally triggered on to discharge ESD current. Therefore, it can have a high ESD robustness in a small layout area.

Abstract translation: 静电放电保护电路。 静电放电保护电路利用多指栅极接地NMOS的非均匀触发。 具有触发电位的手指的源极耦合到所有其他多指栅极 - 接地NMOS结构的所有寄生双极晶体管的基极端子。 因此，具有被触发的可能性的手指可以用作在ESD事件期间触发其他指状装置的触发装置。 通过使用这种方法，可以均匀地触发ESD指令，以多指布局结构实现的ESD保护NMOS或PMOS，以放电ESD电流。 因此，它可以在小布局区域具有高ESD稳定性。