发明授权
- 专利标题： Semiconductor device with low power consumption memory circuit
- 专利标题（中）： 具有低功耗存储电路的半导体器件
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申请号： US10274985申请日： 2002-10-22
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公开(公告)号： US06657911B2公开(公告)日： 2003-12-02
- 发明人: Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
- 申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
- 优先权： JPP2001-324357 20011023
- 主分类号： G11C700
- IPC分类号： G11C700
摘要：
The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state. The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.
公开/授权文献
- US20030076705A1 Semiconductor device 公开/授权日：2003-04-24