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公开(公告)号：US20060268647A1
公开(公告)日：2006-11-30
申请号：US11500339
申请日：2006-08-08
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
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公开(公告)号：US08711607B2
公开(公告)日：2014-04-29
申请号：US13110068
申请日：2011-05-18
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US07646662B2
公开(公告)日：2010-01-12
申请号：US12325783
申请日：2008-12-01
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路具有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US07961545B2
公开(公告)日：2011-06-14
申请号：US12629981
申请日：2009-12-03
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US20100080046A1
公开(公告)日：2010-04-01
申请号：US12629981
申请日：2009-12-03
IPC分类号： G11C5/14 , G11C11/413
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US07474584B2
公开(公告)日：2009-01-06
申请号：US11833190
申请日：2007-08-02
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US06657911B2
公开(公告)日：2003-12-02
申请号：US10274985
申请日：2002-10-22
IPC分类号： G11C700
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state. The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.
摘要翻译： 本发明涉及一种整合逻辑电路和SRAM电路的系统LSI。 更具体地说，本发明涉及能够减少待机状态下的漏电流和功耗的半导体装置。系统LSI中的逻辑电路设置有电源开关，以便在断开时切断开关 待机，减少漏电流。 同时，SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US20090097302A1
公开(公告)日：2009-04-16
申请号：US12325783
申请日：2008-12-01
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US06914803B2
公开(公告)日：2005-07-05
申请号：US10671513
申请日：2003-09-29
IPC分类号： G11C11/41 , G11C5/14 , G11C11/34 , G11C11/413 , G11C11/417 , G11C11/418 , H01L29/94 , G11C11/00
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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公开(公告)号：US20080019205A1
公开(公告)日：2008-01-24
申请号：US11833190
申请日：2007-08-02
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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