A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.