公开(公告)号：US08604865B2

公开(公告)日：2013-12-10

申请号：US13478485

申请日：2012-05-23

Applicant: Nicolas Pillin ,  David A. Kamp

Inventor： Nicolas Pillin ,  David A. Kamp

IPC: H03K17/687

CPC classification number: G06K19/0723 ,  H01L29/78

Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.

Abstract translation: RFID应答器包括电子电路和天线，该电子电路集成在p型衬底中，并且包括由PMOS晶体管形成的调制器，该PMOS晶体管的漏极电连接到天线的焊盘和源，连接到地 的电子电路布置在设置在p型衬底中的n型阱中。 PMOS晶体管具有由驱动电路驱动的栅极，该驱动电路被布置为提供至少一个负电压，该负电压足够低以响应由该电子电路的逻辑单元提供的控制信号而导通该PMOS晶体管。

公开(公告)号：US20130320096A1

公开(公告)日：2013-12-05

申请号：US13488765

申请日：2012-06-05

Applicant: James SPRINGER ,  David A. KAMP

Inventor： James SPRINGER ,  David A. KAMP

IPC: G06K19/073

CPC classification number: G06K19/0701 ,  G06K19/0723

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract translation: RFID应答器芯片包括至少一个用于拾取和发送射频信号的天线，整流器，用于在拾取的射频信号的整流电压下在至少一个电容器上存储电荷，上电复位电路 如果整流的电压电平小于用于操作逻辑单元的上电复位电路的上电复位或唤醒电压，则将逻辑单元维持在复位状态。 RFID应答器芯片还包括非易失性存储器，其中存储一个或多个修整值。 所述非易失性存储器直接连接到上电复位电路，以能够提供至少一个修整值，以在低于唤醒电压电平的整流电压电平下修整上电复位电路。

公开(公告)号：US08422317B2

公开(公告)日：2013-04-16

申请号：US12945168

申请日：2010-11-12

Applicant: David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

Inventor： David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

IPC: G11C7/22 ,  G11C5/14

CPC classification number: G08B13/06

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit formed by at least a NVM cell and a sensor activated by a physical or chemical action or phenomenon, the NVM unit arranged for storing in the NVM cell, by using electrical power of the electrical stimulus pulse, a bit of information relative to detection by the sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal and a base terminal of the NVM unit with at least a given set voltage.

Abstract translation: 所述自供电检测装置包括由至少NVM单元形成的非易失性存储器（NVM）单元和由物理或化学作用或现象激活的传感器，所述NVM单元被布置成存储在NVM单元中，通过使用电 电刺激脉冲的功率，在自动检测装置的检测模式期间相对于传感器检测的一点信息，至少一个物理或化学作用或现象至少具有给定的强度，或 并且产生在至少给定的设定电压之间提供在NVM单元的设定控制端子和基极端子之间的电压刺激信号。

公开(公告)号：US20110119017A1

公开(公告)日：2011-05-19

申请号：US12945168

申请日：2010-11-12

Applicant: David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

Inventor： David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

IPC: G06F15/00

CPC classification number: G08B13/06

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed by at least a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, the NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of the NVM unit with at least a given set voltage. In a first principal embodiment, the self-powered detection device comprises a read circuit (56) and a switch (58,60) arranged in the electrical path between the ground (GND) of the sensor and a terminal of the NVM cell and having its control gate (G) electrically connected to the set control terminal (SET), said switch being ON when its control gate receives in a detection mode said voltage stimulus signal and the self-powered detection device being arranged so that this switch is OFF in the read mode. In a second principal embodiment, a reset circuit is electrically connected in a reset mode to the base terminal (SET *) of the NVM unit for resetting said NVM cell and the self-powered detection device comprises a switch (58,60) arranged between the ground (GND) of the sensor and this base terminal and having its control gate (G) electrically connected to the set control terminal (SET), said switch being ON when its control gate receives in a detection mode said voltage stimulus signal and the self-powered detection device being arranged so that this switch is OFF in the reset mode.

Abstract translation: 所述自供电检测装置包括由至少NVM单元形成的非易失性存储器（NVM）单元（52）和由物理或化学作用或现象激活的传感器，所述NVM单元被布置成存储在所述 NVM单元通过使用所述电刺激脉冲的电力，在自供电检测装置的检测模式期间相对于所述传感器的检测的一点信息，施加至少一个物理或化学作用或现象 它具有至少给定的强度或强度，并且导致在至少一个给定的设定电压之间提供在NVM单元的设定控制端（SET）和基端（SET *）之间的电压刺激信号。 在第一主要实施例中，自供电检测装置包括布置在传感器的接地（GND）和NVM单元的端子之间的电气路径中的读取电路（56）和开关（58,60），并具有 其控制栅极（G）电连接到设定控制端（SET），所述开关当其控制栅极在检测模式下接收所述电压刺激信号时，所述开关导通，并且所述自供电检测装置被布置成使得所述开关在 读取模式。 在第二主要实施例中，复位电路以复位模式电连接到NVM单元的基座（SET *），用于复位所述NVM单元，并且所述自供电检测装置包括布置在所述NVM单元之间的开关（58,60） 传感器的接地端（GND）和该基极端子，并且其控制栅极（G）电连接到设定控制端子（SET），当控制栅极在检测模式下接收时，所述开关导通，所述电压刺激信号和 自动供电的检测装置被布置成使得该复位模式下该开关为OFF。

公开(公告)号：US06760246B1

公开(公告)日：2004-07-06

申请号：US10136210

申请日：2002-05-01

Applicant: David A. Kamp ,  Alan D. DeVilbiss

Inventor： David A. Kamp ,  Alan D. DeVilbiss

IPC: G11C1122

CPC classification number: G11C11/22

Abstract: A ferroelectric field effect transistor (FET) has a gate, source, drain, and substrate. A negative voltage is applied to the gate. Ground potential is applied to the source, drain, and substrate. The negative voltage has a magnitude at least equal to the coercive voltage of the FET. A positive voltage is then applied to the gate. Ground potential is applied to the source and substrate. The positive voltage is no less than the coercive voltage. Either a positive voltage or a ground potential is applied to the drain to write a logic state to the FET. A voltage is applied to the gate. Ground potential is applied to the source. A positive voltage is applied to the drain. The drain current is measured and compared to a compare current. The relative size of the drain current compared to the compare current is indicative of the stored logic state in the FET.

Abstract translation: 铁电场效应晶体管（FET）具有栅极，源极，漏极和衬底。 向栅极施加负电压。 接地电位施加到源极，漏极和衬底。 负电压的幅度至少等于FET的矫顽电压。 然后将正电压施加到栅极。 接地电位施加到源极和衬底上。 正电压不小于矫顽电压。 将正电压或接地电位施加到漏极，以将逻辑状态写入FET。 电压被施加到门。 接地电位被施加到源。 向漏极施加正电压。 测量漏极电流并将其与比较电流进行比较。 与比较电流相比，漏极电流的相对大小表示FET中存储的逻辑状态。

公开(公告)号：US06201731B1

公开(公告)日：2001-03-13

申请号：US09322490

申请日：1999-05-28

Applicant: David A. Kamp ,  Gary F. Derbenwick ,  George B. Coombe ,  Troy A. Meester

Inventor： David A. Kamp ,  Gary F. Derbenwick ,  George B. Coombe ,  Troy A. Meester

IPC: C11C1604

CPC classification number: G11C11/22

Abstract: A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.

Abstract translation: 铁电破坏性读出存储器系统包括电源，包括存储单元的存储器阵列和用于向存储器阵列施加信号的逻辑电路。 每当在所述电源中检测到低功率状况时，干扰防止电路可以防止由于低功率状况引起的非预期电压扰乱存储单元。 干扰防止电路也会使逻辑电路的操作停止足以允许完成重写周期的时间，从而防止数据被重写的损失。

公开(公告)号：US08702008B2

公开(公告)日：2014-04-22

申请号：US13488765

申请日：2012-06-05

Applicant: James Springer ,  David A. Kamp

Inventor： James Springer ,  David A. Kamp

IPC: G06K19/06

CPC classification number: G06K19/0701 ,  G06K19/0723

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract translation: RFID应答器芯片包括至少一个用于拾取和发送射频信号的天线，整流器，用于在拾取的射频信号的整流电压下在至少一个电容器上存储电荷，上电复位电路 如果整流的电压电平小于用于操作逻辑单元的上电复位电路的上电复位或唤醒电压，则将逻辑单元维持在复位状态。 RFID应答器芯片还包括非易失性存储器，其中存储一个或多个修整值。 所述非易失性存储器直接连接到上电复位电路，以能够提供至少一个修整值，以在低于唤醒电压电平的整流电压电平下修整上电复位电路。

公开(公告)号：US08422293B2

公开(公告)日：2013-04-16

申请号：US12945138

申请日：2010-11-12

Applicant: David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

Inventor： David A. Kamp ,  Filippo Marinelli ,  Thierry Roz

IPC: G11C16/22

CPC classification number: G08B13/06 ,  E05B39/00 ,  E05B45/06 ,  E05B51/023 ,  E05B67/22 ,  E05B2047/0058 ,  E05B2047/0062 ,  E05B2047/0064 ,  G08B29/181

Abstract: The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

Abstract translation: 所述自供电检测装置包括非易失性存储单元和由物理或化学作用或现象激活的传感器，所述传感器形成能量收集器，其将能量从物理或化学作用或现象转换成电刺激脉冲，所述存储器单元 布置成通过使用电刺激脉冲的电力来存储与传感器相关的至少第一物理或化学作用或现象的至少一点信息。 非易失性存储单元包括具有控制栅极的FET晶体管，限定第一输入的第一扩散和限定第二输入的第二扩散。 当在检测模式中，它在设定端子上接收由第一物理或化学作用或现象产生的电压刺激信号时，该FET晶体管从其初始逻辑状态被设置为其写入逻辑状态。

公开(公告)号：US20110110171A1

公开(公告)日：2011-05-12

申请号：US12620365

申请日：2009-11-17

Applicant: David A. KAMP ,  Filippo MARINELLI ,  Thierry ROZ

Inventor： David A. KAMP ,  Filippo MARINELLI ,  Thierry ROZ

IPC: G11C7/20

CPC classification number: E05B39/00

Abstract: The external event detection device comprises an electronic unit (22) and an external event sensor (16), the electronic unit having at least a non-volatile memory cell (24, T1) in which data relative to at least one external event detected by the external event sensor can be stored. According to the invention, the external event sensor defines an energy harvester that transforms energy from said at least one external event into electrical energy contained in an electrical stimulus pulse provided to the electronic unit. The electronic unit is arranged for storing said data by using only the electrical energy contained in the electrical stimulus pulse. In particular, the non-volatile memory cell is directly set to its written logical state from its initial logical state by the electrical stimulus pulse provided by said energy harvester. In a preferred embodiment, the electronic unit further comprises a set circuit (26) comprising a second FET transistor (T2) arranged between the ground of the electronic unit and the drain of a first FET transistor (T1) defining the non-volatile memory cell, this switch having a control gate connected to the control gate of the first FET transistor. The second FET transistor is turned on when an electrical stimulus pulse is provided to the electronic unit, connecting the drain (DRN) of the first FET transistor (T1) to ground and thus allowing the secure setting of the non-volatile memory cell.

Abstract translation: 外部事件检测装置包括电子单元（22）和外部事件传感器（16），所述电子单元至少具有非易失性存储单元（24，T1），其中相对于由 可以存储外部事件传感器。 根据本发明，外部事件传感器限定能量收集器，其将来自所述至少一个外部事件的能量转换成提供给电子单元的电刺激脉冲中包含的电能。 电子单元被布置成通过仅使用包含在电刺激脉冲中的电能来存储所述数据。 特别地，非易失性存储单元通过由所述能量收集器提供的电刺激脉冲从其初始逻辑状态直接设置为其写入的逻辑状态。 在优选实施例中，电子单元还包括设置电路（26），其设置在第二FET晶体管（T2）之间，第二FET晶体管（T2）布置在电子单元的接地和限定非易失性存储单元的第一FET晶体管（T1）的漏极之间 该开关具有连接到第一FET晶体管的控制栅极的控制栅极。 当向电子单元提供电刺激脉冲时，第二FET晶体管导通，将第一FET晶体管（T1）的漏极（DRN）接地，从而允许非易失性存储单元的安全设置。

公开(公告)号：US06658608B1

公开(公告)日：2003-12-02

申请号：US09400210

申请日：1999-09-21

Applicant: David A. Kamp ,  Gary F. Derbenwick

Inventor： David A. Kamp ,  Gary F. Derbenwick

IPC: G11C2900

CPC classification number: G11C29/028 ,  G11C11/22 ,  G11C29/50

Abstract: A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.

Abstract translation: 铁电集成电路存储器件包括：多个存储单元，每个存储单元包括铁电材料，多个导线，每个导体线连接到或连接到选定的一个存储单元; 驱动电路，用于将预定电压预定时间施加到所选择的导线中，所述预定电压和时间是对所述存储单元执行写或读功能所需的正常电压和时间，从所述组中选择的功能 将逻辑状态写入所选存储单元，并读取所选存储单元; 以及模式控制电路，其响应于外部信号用于调整所述预定电压或所述预定时间以执行从由以下组成的组中选择的操作：所选择的存储器单元的部分读取和所选存储单元的部分写入; 并向存储单元施加铁电应力。 将已知的逻辑状态写入存储器单元，单元被加热，然后读取以提供指示每个存储器单元的过早故障的可能性的输出数据。 通过对与逻辑状态相反的逻辑状态相对应的单元反复施加电压，在单元被写入之前或之后对电池施加铁电应力。