An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.